EDN Access

Synthesis Shoot-Out at the EDN Corral

Table 4: Synopsys FPGA Express results

Speed emphasis, low effort
  Front-end tools Back-end (Xilinx Alliance M1) tools
File Compile time1 Synthesize time2/optimize time3 Place-and-route time4 Clock frequency Clock 2 frequency (MHz)5 CLB flip-flop count (MHz)5 I/O-buffer flip-flop count Four-LUT count6 Three-LUT count6 Estimated gate count7 CLB count8
BACKFIFO.VHD 00:00:06 00:16:30 00:10:01 Not applicable 3.09 524 0 831 316 (240) 8584 510 (16%)
HOST_IF.VHD 00:00:05 00:08:39 00:05:46 8.53 13.61 150 72 445 48 (9) 4520 249 (7%)
HOSTFIRD.VHD 00:00:04 00:08:03 00:05:39 14.21 9.95 507 16 406 278 (241) 5740 331 (10%)
HOSTFIWR.VHD 00:00:04 00:08:59 00:06:13 5.86 10.43 491 32 424 265 (233) 5826 359 (11%)
INTBUFF.VHD 00:00:03 00:00:17 00:00:32 Not applicable Not applicable 0 0 0 0 0 0 (0%)
MEMTOP.VHD 00:00:02 00:01:51 00:04:03 Not applicable 14.82 31 18 126 14 1113 65 (2%)
TOPLEVEL.VHD 00:00:02 01.29:28 01:03:39 13.02 2.46 1782 56 2547 1016 (733) 28,890 1586 (50%)
X1.VHD 00:00:03 00:02:08 00:04:33 Not applicable Not applicable 0 0 235 47 1831 120 (3%)
X2.VHD 00:00:03 00:01:41 00:04:32 Not applicable Not applicable 0 0 184 (1) 5 1722 95 (3%)
BACKFIRM.VHD 00:00:03 00:00:24/00:00:25 00:04:15 Not applicable 6.07 12 0 176 12 5006 91 (2%)
HOFIRDRM.VHD 00:00:02 00:00:13/00:00:17 00:03:34 13.1 10.49 11 0 104 0 4402 54 (1%)
HOFIWRRM.VHD 00:00:03 00:00:15/00:00:23 00:03:34 4.3 4.46 11 0 117 1 4484 60 (1%)
TOPLEVRM.VHD 00:00:03 00:05:13/00:10:51 00:15:51 9.03 3.61 260 42 1218 107 (11) 21,995 636 (20%)
Speed emphasis, high effort
File Compile time1 Synthesize time2/optimize time3  Place-and-route time4 Clock 1 frequency (MHz)5 Clock 2 frequency (MHz)5 CLB flip-flop count I/O-buffer flip-flop count Four-LUT count6 Three-LUT count6 Estimated gate count7 CLB count8
BACKFIFO.VHD 00:00:06 00:20:56 00:10:01 Not applicable 3.09 524 0 831 316 (240) 8584 510 (16%)
HOST_IF.VHD 00:00:05 00:09:17 00:05:21 10.69 6.92 150 72 399 51 (9) 4258 221 (7%)
HOSTFIRD.VHD 00:00:04 00:08:45 00:05:40 28.97 13.92 507 16 400 277 (241) 5700 328 (10%)
HOSTFIWR.VHD 00:00:04 00:08:55 00:05:59 13.52 26.31 491 32 413 267 (233) 5769 359 (11%)
INTBUFF.VHD 00:00:03 00:00:16 00:00:31 Not applicable Not applicable 0 0 0 0 0 0 (0%)
MEMTOP.VHD 00:00:02 00:01:47 00:03:54 Not applicable 15.92 31 18 91 8 876 48 (1%)
TOPLEVEL.VHD 00:00:02 01.34:46 01:01:04 10.69 3.23 1782 56 2479 (1) 972 (732) 28,283 1551 (49%)
X1.VHD 00:00:03 00:04:10 00:04:26 Not applicable Not applicable 0 0 232 42 1791 119 (3%)
X2.VHD 00:00:03 00:01:39 00:04:38 Not applicable Not applicable 0 0 177 (1) 4 1676 91 (2%)
BACKFIRM.VHD 00:00:03 00:00:21/00:00:33 00:04:19 Not applicable 6.07 12 0 176 12 5006 91 (2%)
HOFIRDRM.VHD 00:00:02 00:00:16/00:00:18 00:03:29 18.84 4.77 11 0 93 2 4345 48 (1%)
HOFIWRRM.VHD 00:00:03 00:00:16/00:00:25 00:03:30 6.33 8.15 11 0 106 00 4414 54 (1%)
TOPLEVRM.VHD 00:00:03 00:05:20/00:18:00 00:15:21 6.6 3.74 260 42 1203 92 (10) 21,842 632 (20%)
Area emphasis, low effort
File Compile time1 Synthesize time2/optimize time3  Place-and-route time4 Clock 1 frequency (MHz)5  Clock 2 frequency (MHz)5 CLB flip-flop count I/O-buffer flip-flop count Four-LUT count6 Three-LUT count6 Estimated gate count7 CLB count8
BACKFIFO.VHD 00:00:06 00:13:47 00:09:55 Not applicable 8.78 524 0 807 312 (240) 8422 428 (13%)
HOST_IF.VHD 00:00:05 00:06:37 00:05:27 12.44 11.17 150 72 374 52 (9) 4112 204 (6%)
HOSTFIRD.VHD 00:00:04 00:06:42 00:05:41 9 7.19 507 16 399 276 (241) 5689 327 (10%)
HOSTFIWR.VHD 00:00:04 00:06:41 00:06:00 14.61 24.94 491 32 402 269 (233) 5712 320 (10%)
INTBUFF.VHD 00:00:03 00:00:18 00:00:31 Not applicable Not applicable 0 0 0 0 0 0 (0%)
MEMTOP.VHD 00:00:02 00:01:54 00:03:55 Not applicable 5.88 31 18 94 8 894 49 (1%)
TOPLEVEL.VHD 00:00:02 01:02:05 01:00:22 5.84 3.64 1782 56 2438 (5) 974 (732) 28,022 1517 (48%)
X1.VHD 00:00:03 00:01:37 00:04:19 Not applicable Not applicable 0 0 186 37 1492 94 (2%)
X2.VHD 00:00:03 00:01:14 00:04:33 Not applicable Not applicable 0 0 172 (5) 11 1653 88 (2%)
BACKFIRM.VHD 00:00:03 00:00:57/00:00:25 00:04:16 Not applicable 12.35 12 0 167 12 4952 86 (2%)
HOFIRDRM.VHD 00:00:02 00:00:19/00:00:15 00:03:29 16.2 4.57 11 0 94 6 4369 49 (1%)
HOFIWRRM.VHD 00:00:03 00:00:17/00:00:17 00:03:33 6.63 11.45 11 0 110 3 4451 58 (1%)
TOPLEVRM.VHD 00:00:03 00:05:54/00:08:14 00:15:33 3.25 3.08 260 42 1195 (5) 124 (10) 21,908 624 (19%)
Area emphasis, high effort
File Compile time1 Synthesize time2/optimize time3  Place-and-route time4 Clock 1 frequency (MHz)5  Clock 2 frequency (MHz)5 CLB flip-flop count I/O-buffer flip-flop count Four-LUT count6 Three-LUT count6 Estimated gate count7 CLB count8
BACKFIFO.VHD 00:00:06 00:16:34 00:10:02 Not applicable 8.78 524 0 807 312 (240) 8422 428 (13%)
HOST_IF.VHD 00:00:05 00:07:33 00:05:03 9.89 7 150 72 339 43 (9) 3862 192 (6%)
HOSTFIRD.VHD 00:00:04 00:07:48 00:05:35 27.03 18.42 507 16 395 274 (241) 5656 325 (10%)
HOSTFIWR.VHD 00:00:04 00:07:42 00:05:52 10.94 29.34 491 32 397 268 (233) 5677 318 (10%)
INTBUFF.VHD 00:00:03 00:00:14 00:00:36 Not applicable Not applicable 0 0 0 0 0 0 (0%)
MEMTOP.VHD 00:00:02 00:01:36 00:03:49 Not applicable 10.64 31 18 84 7 829 44 (1%)
TOPLEVEL.VHD 00:00:02 01:15:10 00:59:00 10.21 2.6 1782 56 2383 (1) 973 (732) 27,711 1497 (47%)
X1.VHD 00:00:03 00:03:21 00:04:15 Not applicable Not applicable 0 0 186 37 1492 94 (2%)
X2.VHD 00:00:03 00:01:15 00:04:40 Not applicable Not applicable 0 0 164 12 1640 84 (2%)
BACKFIRM.VHD 00:00:03 00:00:33/00:00:27 00:04:16 Not applicable 12.35 12 0 167 12 4952 86 (2%)
HOFIRDRM.VHD 00:00:02 00:00:15/00:00:14 00:03:27 24.48 4.38 11 0 88 1 4310 46 (1%)
HOFIWRRM.VHD 00:00:03 00:00:15/00:00:19 00:03:33 3.61 4.23 11 0 104 0 4402 53 (1%)
TOPLEVRM.VHD 00:00:03 00:05:22/00:16:43 00:14:49 4.45 3.20 260 42 1164 114 (10) 21,707 615 (19%)
Notes:

All times are in hh:mm:ss (hours:minutes:seconds) format and timed using a stopwatch; LUT=look-up table; CLB=configurable logic block.

1 Includes "analyze" delay; measured by noting system clock time when begun and then comparing against .EXP file time stamp on completion.
2 Includes "elaborate" delay; measured by noting system clock time when begun and then comparing against .EXP file time stamp on completion.
3 Includes "optimize," "map," and "export-netlist" delays; measured by noting system clock time when begun and then comparing against .EXP file time stamp on completion.
4 Includes "translate," "map," and "place-and-route" delays from DOS-batch-file TIME captures.
5 Obtained by inserting "NET xxx PERIOD = 30;" statements in each .PCF file and then running Xilinx's TRCE utility.
6 Number insideparentheses (if shown) is number of LUTs used as routing resources.
7 Does not include JTAG logic for I/O buffers.
8 Number inside parentheses is percentage of total available CLBs the design consumes.

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