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September 11, 1998
Fast comparators find their niche in linear applications
Comparators don’t “just compare” in the same way that op
amps don’t “just amplify.” A collection of application circuits
demonstrates just how flexible and useful a high-speed comparator can be.
Jim Williams, Linear Technology Corp
Comparators may be the most underrated and under-used monolithic linear
components—an unfortunate fact because comparators are also among the most flexible
and universally applicable components. The comparator's lack of recognition is largely
thanks to the IC op amp, whose versatility allows it to dominate analog design. Although
you can look at comparators as devices that crudely express an analog signal in digital
form, specifically as a 1-bit A/D converter, this viewpoint is wastefully constrictive.
Comparators, and high-speed comparators in particular, can implement linear-circuit
functions that are as sophisticated as any op-amp-based circuit. A recently introduced
comparator, the LT1394 (see sidebar "High-speed comparator
pairs high speed with stability"), combined with the precautionary tales for all
high-speed components, permits fast linear-circuit functions that are difficult or
impractical to perform using other approaches.
Some of the following applications represent the state of the art for a particular
circuit function. Others show simplified or improved ways to implement standard functions
by using the comparator's easily accessible speed. All of the circuits have been carefully
(and painfully) worked out and should serve as good ideas for high-speed comparators and
their uses.
Switchable-output crystal oscillator
In Figure 1, a basic oscillator configuration with
additional circuitry permits logic commands to electronically switch between crystals.
Oscillation is possible only when one of the logic inputs is high. The 1-kOhm resistors at
the comparator's input set the dc bias point. The 2-kOhm, 75-pF path sets up phase-shifted
feedback, and the circuit resembles a wideband unity-gain follower at dc. The selected
crystal path provides resonant positive feedback, and stable oscillation occurs. The basic
circuit supports oscillation frequencies from 1 to 10 MHz. At higher than 10 MHz, AT-cut
crystals operate in overtone mode, and oscillation can occur at multiples of the desired
frequency. If you include the optional damper network at the comparator input, the circuit
can support oscillation frequencies as high as 30 MHz. This network rolls off gain at high
frequencies, ensuring proper operation.
Temperature-compensated crystal oscillator
Figure 2 depicts a temperature-compensated crystal
oscillator. This circuit reduces the oscillator's temperature drift by inserting a
temperature-dependent compensatory correction into the crystal's frequency-trimming
network. This open-loop correction technique relies on matching the oscillator's
frequency-versus-temperature characteristic, which is repeatable.
The LT1394 and associated components form the crystal oscillator, which operates
similarly to the circuit in Figure 1. The LM134, a
temperature-dependent current source, biases IC1. The dc level at the positive
input of IC1 is a function of the LT1004's reference voltage and the LM134's
temperature-dependent voltage. IC1 amplifies the resultant dc level at its
positive input by a gain of approximately 7. The circuit derives the LT1004's negative
bias voltage from the oscillator's output, thereby maintaining the circuit's single-supply
operation. This arrangement de-livers temperature-dependent bias to the varactor diode,
causing a scaled variation in the crystal's resonance versus ambient temperature. The
varactor's bias-dependent capacitance shifts the crystal's frequency to complement the
circuit's temperature drift. This compensation provides a simple, linear, first-order
correction.
The circuit corrects for the crystal's -70-ppm frequency shift over 0 to 70°C to
within a few ppm. The frequency-set trim also biases the varactor, allowing accurate
output-frequency setting. Even better compensation is possible by including nonlinear
terms in the temperature-to-voltage conversion.
Voltage-controlled crystal oscillator
Another variant of the basic crystal oscillator permits voltage tuning of the output
frequency (Figure 3). Such voltage-controlled crystal
oscillators are useful when a slight variation of a stable carrier is necessary. The most
common application is to provide a 4XNTSC subcarrier tunable oscillator suitable for phase
locking.
This circuit again configures the comparator and associated components as a crystal
oscillator. The tuning input, VIN, biases the varactor diode. The
tuning-network arrangement allows a 0 to 5V drive to provide a reasonably symmetric and
broad tuning range around the 14.31818-MHz center frequency. The capacitor CSELECT
sets the tuning bandwidth. You should select the value of this capacitor to complement the
loop response in phase-locking applications. The tuning deviation from the 4XNTSC
14.31818-MHz center frequency exceeds approximately ±240 ppm (±4 kHz) for a 0 to 5V
input.
Tunable clock-skew generator
It is sometimes necessary to generate pairs of identical clock signals that are
phase-skewed in time. Further, you may desire to set the amount of time skew via a tuning
voltage. Figure 4a's circuit performs both functions by
using comparators to digitize phase information from a varactor-tuned time-domain bridge.
A 0 to 2V control signal provides approximately ±10-nsec of output skew. The input drives
the CMOS inverters, which in turn deliver noninverting drive to the bridge network (Trace
A, Figure 4b). (The bridge, which essentially comprises
two RC sections, responds in ramp fashion at both of its outputs; Trace B is the bridge's
"fixed" output, and Trace C is its "skewed" output.) A varactor diode,
which receives bias from IC1 and hence from the control input, tunes the
capacitance of the "skewed" half of the bridge.
The comparators, which the circuit references to one-half the supply voltage, trigger
when their positive inputs exceed the reference point. Traces D and E are the outputs of
IC2 and IC3, respectively. The imbalance in the bridge's RC time
constants, which the voltage input controls, determines the time skew of the comparators'
responses. The diode-resistor network across the 2.5-kOhm bridge resistor compensates for
ramp-induced variation of varactor capacitance, enhancing control symmetry.
Q1 and associated components form a simple voltage-boost stage, enabling IC1
to supply adequate varactor bias. The bridge's ratiometric operation permits almost
100-to-1 power-supply rejection ratio over a 4.5 to 5.5V input range. To trim this
circuit, put in 2V and adjust the 2-kOhm potentiometer for 10 nsec of skew in the outputs.
Over a 0 to 2V range, output skew varies continuously from -10 nsec through 0, to 10 nsec.
Fast, high-impedance, variable-threshold trigger
Instrumentation applications frequently require a fast trigger with a variable
threshold. A high-impedance input is also often necessary (Figure
5). Comparator IC1 is the basic trigger; the VTRIGGER input sets
the threshold at IC1's negative input. Source follower Q1 provides
high impedance with approximately 2 pF of input capacitance and 50 pA of bias current.
Normally, Q1's source bias point is uncertain and drifty, but stabilization
techniques eliminate this concern.
IC1 measures filtered versions of Q1's gate and source voltages.
IC2's output biases Q2, forcing Q1's channel current to
whatever value is necessary to equalize IC2's inputs and, hence, Q1's
gate and source voltages. IC2's input filtering and roll-off are far slower
than input frequencies of interest but do not interfere with the circuit's main signal
path. The 330-pF capacitor prevents fast edges that couple through Q2's
collector-base junction from influencing IC2's operation.
Q1 contributes negligible timing error to minimize overall delay; Q1's
source lags behind the input by only 300 psec. The delay from the input to IC1's
output is approximately 8 nsec.
High-speed adaptive-trigger circuit
Line and fiber-optic receivers often require an adaptive trigger to compensate for
variations in signal amplitude and dc offsets. The circuit in Figure
6 triggers on 2- to 175-mV signals from 100 Hz to 45 MHz and operates from one 5V
rail. IC1, operating at a gain of 15, provides wideband ac gain. The output of
this stage biases a two-way peak detector comprising Q1 through Q4.
Q2's emitter capacitor stores the maximum peak, and Q4's emitter
capacitor retains the minimum excursion. The dc value of the midpoint of IC1's
output signal appears at the junction of the 500-pF capacitor and the 3-MOhm resistors.
This point sits midway between the signal's excursions, regardless of absolute amplitude.
IC2 buffers this signal-adaptive voltage to set the trigger voltage at IC3's
positive input. IC1's output directly biases the comparator's negative input.
The comparator's output, which is the circuit's output, is unaffected by
greater-than-85-to-1 signal-amplitude variations. Bandwidth limiting in IC1
does not affect triggering because the adaptive-trigger threshold varies accordingly,
maintaining circuit output. Split-supply versions of this circuit can achieve bandwidths
as high as 50 MHz with wider input operating ranges (Reference 1).
An 18-nsec, 500-mV sensitivity comparator
The ultimate limitation on comparator sensitivity is available gain. Unfortunately,
increasing gain invariably involves giving up speed. In a fast comparator, the
gain-versus-speed trade-off is usually a practical compromise that satisfies most
applications. However, some situations require more sensitivity (for example, higher gain)
with minimal impact on speed. Adding a differential preamplifier ahead of the comparator,
IC3, increases the gain (Figure 7a). This
addition permits 500-µV comparisons in 18 nsec.
A parallel-path dc-stabilization approach eliminates preamplifier drift as an error
source. IC1 is the differential preamplifier, operating at a gain of 100, and
the circuit ac-couples the output of IC1 to IC3. IC1 has
poorly defined dc characteristics, necessitating some dc correction. IC2A and
IC2B, which operate at a differential gain of 100, provide this function. They
differentially sense a bandlimited version of IC1's inputs and feed dc and
low-frequency amplified information to the comparator. The low-frequency roll-off of IC1's
signal path complements the high-frequency roll-off of IC2A and IC2B.
The summation of these two signal channels at the comparator inputs results in a flat
response from dc to high frequency.
Figure 7b shows the circuit's propagation delay. The
output responds in 18 nsec to a 500-µV overdrive on a 1-µV step. As you might expect,
propagation delay decreases at higher overdrives; the output responds in 15 nsec to a
1000-µV overdrive. IC1's noise limits usable sensitivity.
Voltage-controlled delay
The ability to set a precise, predictable delay has broad application in pulse
circuitry. The circuit configuration in Figure 8a produces
a 0- to 300-nsec delay from a corresponding 0 to 3V control voltage. This circuit takes
advantage of the comparator's speed and of the clean dynamics of an emitter-switched
current source.
Q1 and Q2 form a current source that charges the 1000-pF
capacitor. When the trigger input is high (Trace A, Figure 8b)
both Q3 and Q4 are on. The current source is off, and Q2's
collector (Trace B) is at ground. The latch input prevents the comparator from responding,
and its output remains high. A low trigger input disables the comparator's latch input,
and its output drops low. Q4's collector (Trace C) lifts, and Q2
comes on, delivering constant current to the 1000-pF capacitor (Trace B). The circuit
compares the resulting linear ramp at the comparator's positive input to the
delay-programming- voltage input. When a crossing occurs, the comparator goes high (Trace
D). How long the comparator stays low is directly proportional to the delay programming
voltage. The fast switching and ramp linearity permit 1-nsec accuracy and 100-psec
repeatability.
A high-speed expansion of the current source turn-on details the clean switching (Figure 8c). Q4 goes off within 2 nsec of the
trigger's input dropping low (Trace A), enabling the current source. (Q2's
emitter is Trace C.) Concurrently, the 1000-pF capacitor's ramp (Trace B) begins. The
LT1394's output (Trace D) drops low about 7 nsec later, returning high after crossing, in
this case, a relatively low programming voltage.
To calibrate this circuit, apply a trigger input and 3V to the programming input.
Adjust the 100V trim for a 300-nsec width at the LT1394's output.
10-nsec sample-and-hold
Figure 9's 10-nsec S/H circuit applies the
voltage-programmable-delay circuit of Figure 8a. This S/H
circuit is fast, but it works only with repetitive signals. IC1 drives the
input of differential integrator IC2. Feedback from the integrator back to IC1
closes a loop around the circuit. In response to an input waveform, IC3
generates a trigger signal for the programmable-delay generator. The output of this delay
generator triggers the 74121 one-shot. The one-shot's Q output produces a 30-nsec pulse,
which drives a logic network along with the Q signal. The two inverter delays in the Q
output's path give its associated gate a duration output shorter than Q's gate. The last
gate subtracts these two signals and generates a 10-nsec spike. The circuit inverts this
spike, and this inverted signal drives IC1's latch pin.
Each time the circuit enables the comparator's latch input, the comparator responds to
the condition of the summing junction at its positive input. If the summing error is
positive, IC2 pulls current. If the error is negative, IC2 sources
current to the junction. After a number of input cycles, IC2's output settles
at a dc value equal to the level that the circuit senses during the sampling interval. The
delay-programming circuit allows you to position the 10-nsec sampling "window"
anywhere on the input waveform.
Subnanosecond delayed-pulse generator
The preceding circuit's 10-nsec-wide sampling window limits sampling speed. Faster
sampling requires narrower pulses. The circuit in Figure 10a
uses an avalanche pulse generator (References 1 and 2) to create
short events. The combination of a controllable, calibrated delay and a fast pulse
generator has broad applicability in fast-sampling circuitry.
C1 and Q1 through Q4 form a delay-programming voltage
identical to the one in Figure 8a. Q5, the
LT1082 switching regulator, and associated components constitute the avalanche pulse
generator. The generator provides an 800-psec pulse with rise and fall times within 250
psec. Pulse amplitude is 10V with a 50 Ohm source impedance.
The pulse generator requires high-voltage bias for operation. The LT1082 switching
regulator forms a high-voltage switched-mode control loop. This regulator
pulse-width-modulates at its 40-kHz clock rate. The circuit rectifies L1's
inductive events and stores the result in the 2-mF output capacitor. The adjustable
resistor-divider provides feedback to the LT1082. The 10-kOhm 1-mF RC network provides
noise filtering.
The circuit applies the high voltage to Q5, which is a 40V breakdown device,
via the R1/C1 combination. You should set the high-voltage
bias-adjust control at the point when the free-running pulses across R2
disappear. This setting puts Q5 slightly below its avalanche point. Applying IC1's
output pulse to Q5's base causes Q5 to go into avalanche. The result
is a quickly rising, fast pulse across R2. IC1 discharges, Q1's
collector voltage falls, and breakdown ceases. IC1 then recharges to just below
the avalanche point. At IC1's next pulse, this action repeats.
Figure 10b, taken with a 3.9 GHz bandpass instrument
(Tektronix 661 with 4S2 sampling plug-in) shows circuit detail. Trace A is IC1's
output, and Trace B is the avalanche pulse. When avalanche occurs, Q5's reverse
base current rises so abruptly that IC1's output cannot directly absorb it. The
100Ohm resistor and the ferrite beads allow C1 to handle the transient load.
Without this network, IC1's positive-going output reverses direction and rings
severely before completing its transition, corrupting avalanche behavior. Even with these
components, artifacts of the avalanche-induced base current are visible in IC1's
output trace.
The avalanche pulse measures 8V high with a 1.2 nsec base. Rise time is 250 psec, and
fall time is 200 psec. In reality, the times are probably slightly faster, because the
oscilloscope's 90-psec rise time influences the measurement.
You may have to select Q5 for avalanche behavior. Although such behavior is
characteristic of the specified device, the manufacturer does not guarantee it. A sample
of 50 Motorola 2N2369s, spread over a 12-year date-code span, yielded 82%. All
"good" devices switched in less than 600 psec. This circuit also requires the
selection of C1 for a 10V amplitude output; the value spread is typically 2 to
4 pF. Ground-plane-type construction with high-speed layout, connection, and termination
techniques is essential to obtain good results from this circuit.
Fast pulse stretcher
A pulse stretcher requires a minimum input-pulse width of 5 to 10 nsec to operate. The
rise and delay times are of the same order. Figure 11a's
circuit is considerably faster. This circuit produces a stretched pulse from a 2-nsec
width input with rise and delay times of 650 psec.
The input pulse causes Q1 to conduct, which charges the timing capacitor, CT.
The input pulse also feeds forward around IC1, via D1, to the
output. Additionally, Q3 buffers CT's potential, which also feeds
forward to the output. IC1 responds to CT's charging by going high,
which turns on Q2 , and augments the output's high state. IC1's
7-nsec delay does not affect output delay or waveshape because the feed-forward paths
"fill in" the dead time before the comparator responds. The output pulse is a
composite of the input and comparator-based responses. The small change in output
amplitude when the input ceases is not deleterious. When the input pulse falls, IC1's
output and, hence, the circuit's output remain high until CT discharges below
IC1's negative input. When IC1 goes low, its inverting output goes
high, pulsing Q4 to pull the output down in 5 nsec.
The feed-forward paths are crucial to the circuit's operation. The effect of D1's
path is easy to understand, but the route that originates at CT is less
obvious. A good way to see the effect of CT's path is to eliminate it. By
opening Q3's base, you can reveal this path's effect (Figure 11b). Trace A is the input pulse; Trace B, the output;
and Trace C, IC1's output. The absence of the CT-based feed-forward
path is evident. The output (Trace B) sags for 8 nsec before the comparator responds and
restores output amplitude.
Evaluating circuit operation requires a fast pulse generator and a wideband
oscilloscope. Figure 11c shows the pulse stretcher's
input/output relationship in a 3.9-GHz sampled bandpass. As in Figure
11b, Trace A is the input pulse, and Trace B is the output. The output amplitude drops
slightly when the input ceases, but the logical high state is maintained. Also visible on
the input's leading edge is a 0.5V-amplitude, 500-psec aberration, which occurs at about
3V into the transition. This aberration results from the circuit's nonlinear input
impedance. The aberration occurs above a logical high level and is acceptable. The output
is delayed from the input by only 650 psec, and rise time is also approximately 650 psec.
The output-pulse width approximately equals the input-pulse width that you add to 25
nsec/pF of CT's value. The ratiometric biasing of IC1's inputs
provides supply-variation immunity of 5V ±5%. An external voltage controls the output
width by biasing IC1's negative input, but this option increases the circuit's
sensitivity to power-supply variations. The minimum input trigger width is 2 nsec to
maintain the programmed output width within 1%.
20-nsec-response overvoltage-protection circuit
You may often need to protect an expensive load from supply overvoltage. Overvoltage
events may result from supply failure or poor transient response. In Figure 12a, Q1, a source follower, receives gate
overdrive bias from the 12V bias supply that saturates Q1. The regulator
driving Q1's drain takes feedback from the source and eliminates Q1's
saturation resistance as an output-impedance term.
IC1 monitors the 3V output that feeds the protected load. Under normal
conditions, IC1's positive input is below its negative input, and its output is
low. Q2 through Q5 are off, and the load receives drive via Q1.
When an overvoltage event occurs, the 3V output rises. IC1 detects this rise,
and its output goes high. Q2 and Q3 come on quickly, pulling down Q1's
gate. Q4 and Q5, which are slower devices, turn on after Q2
and Q3 and shunt Q1's residual output to ground without experiencing
excessive current. A 330Ohm resistor feeds IC1's output to its latch pin, which
causes IC1 to latch high and prevents any output until the overvoltage cause is
corrected. Breaking the latch with the NO reset switch resets the circuit.
The switching optimizes turn-off time (Figure 12b).
Trace A is the 3V output, Trace B is IC1's output, and Trace C is Q1's
gate. The output's amplitude (Trace A) excursion begins just before the second vertical
division. IC1 responds (Trace B) by going high, turning on Q2 and Q3.
This initial turn-on pulls Q1's gate downward, which Trace C shows, arresting
the output's positive-going excursion in 20 nsec. As Q2 pulls charge out of Q1,
gate bias decays. When Q4 and Q5 come on, Q1 is out of
saturation, and the output drops rapidly. The circuit arrests the overvoltage event in 20
nsec and shuts down in 150 nsec. Bypassing Q1's source is optional; this option
slows the overvoltage rise time but also restricts turn-off time. Similarly, the optional
RC filter eliminates noise-induced nuisance tripping at the expense of response time.
- Williams, Jim, "High speed amplifier techniques," Linear Technology Corp,
Application Note 47, August 1991.
- Williams, Jim, "Practical circuitry for measurement and control problems,"
Linear Technology Corp, Application Note 61, August 1994.
The LT1394 comparator has a 200-GHz gain bandwidth and a 7-nsec response time. It
features TTL-compatible complementary outputs, a latch pin, and good dc-input
characteristics. The comparators' outputs directly drive all 5V logic families, including
the high-speed ASTTL, FAST, and HC parts. TTL outputs make the device easy to use in
linear applications for which ECL output levels are often inconvenient.
This comparator is less prone to oscillation and other vagaries than some slower
comparators, even those with slow input signals. The LT1394 is particularly stable in its
linear region. Also, output-stage switching does not appreciably change power-supply
current, further enhancing stability.
Unfortunately, laws of physics dictate that the circuit environment in which the
comparator works must have the proper preparation. Parasitic effects, such as stray
capacitance, ground impedance, and layout, often limit the performance of high-speed
circuitry. To create the best operating environment and make accurate measurements, you
need to know not just how high-speed comparators operate, but also how equipment, cables,
connectors, probes, terminations, and layout affect their performance (Reference A).
Reference
- Williams, Jim, "A seven-nanosecond comparator for single supply operation,"
Application Note 72, Linear Technology Corp, 1998.
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