Programmable Logic Hands-On Project

^{EDN Magazine May 7 and September 11, 1998 Issues}

Overview

Welcome to the EDN Access addendum to my hands-on project published in the May 7, 1998 and September 11, 1998 issues of EDN Magazine. This is a work-in-progress; check back regularly for project updates and new downloadable files. The revision history will keep track of anything that consultant Stephen Wasson and I add, delete or modify.

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Design Documentation

Below you’ll find the detailed specifications for the reference design, in several different formats.

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Schematic-Based Design Files

Consultant Stephen Wasson and I were unable to complete schematic versions of the design in time for benchmarking against the VHDL alternatives in the September 11, 1998 article. I plan to cover schematic-vs-synthesis benchmarking in a future issue of EDN, and when the schematic designs are complete you'll find them here.

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VHDL-Based Design Files

The table that follows contains links for downloading ZIP'd sets of the VHDL source files used with each vendor's compiler (Accolade and Synopsys source files are identical), the batch files I used during front-end compilation and back-end Alliance translate, map, place-and-route and timing analysis routines, and Xilinx Alliance's report files (when UNZIPping, make sure you retain the stored directory structure).

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Enhanced Versions of Tables 2, 3 and 4
(September 11, 1998 Article)

The versions of tables 2, 3 and 4 below contain additional information compared to the versions in the September 11, 1998 article. Specifically, they include the flip-flop, LUT and performance estimate outputs from each synthesis vendor's toolset, prior to running the netlists through Alliance.

Also, due to a printing error, you may have interpreted from the article's table notes that I used a stopwatch to capture all of the front- and back-end process completion times. This is incorrect; the only case where I needed to use a stopwatch was in capturing the Compile Time measurements for Accolade's PeakVHDL in Table 2 (and in this case I reran each compile job 5 times and averaged my stopwatch results to improve accuracy). The remainder of Table 2's times, as well as those for Tables 3 and 4, came from file timestamps, report file outputs and directly from the PC's system clock.

Table 2: Accolade PeakFPGA Results

Table 3: MINC PLSynthesizer Results

Table 4: Synopsys FPGA Express Results

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Synthesis Vendor Optimizations

After I completed my testing, I turned over the VHDL source files to each vendor for optimization purposes. The table that follows contains links to a copy of the letter I sent each vendor, along with their responses as ZIP'd sets of files and directories (when UNZIPping, make sure you retain the stored directory structure). Below it you'll find their respective results tables, along with a description of their optimizations.

Accolade Optimizations

Accolade is still working on their optimizations. Please check back for the results!

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MINC Optimizations

MINC is still working on their optimizations. Please check back for the results!

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Synopsys Optimizations

Synopsys is still working on their optimizations. Please check back for the results!

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Xilinx Optimizations

Soon after I completed my benchmarking, Xilinx began shipping the production release of Alliance version 1.5 (I used version 1.4 for my study). The table below contains links to report files using the synthesis tool-generated netlists I generated for TOPLVLRM.VHD, run through both Alliance 1.4 and 1.5 using a variety of configuration options by Xilinx (when UNZIPping, make sure you retain the stored directory structure). Below it you'll find a description of the computer hardware and operating system platform Xilinx used, as well as tables showing the 1.4-vs-1.5 results for comparison purposes.

The computer platform Xilinx used was a dual-processor Intel Pentium II-400 system, with 512MB of RAM and running Windows NT 4.0 (service pack 3 installed).

Alliance Results (Accolade Netlists For TOPLVLRM.VHD)

Alliance Results (MINC Netlists For TOPLVLRM.VHD)

Alliance Results (Synopsys Netlists For TOPLVLRM.VHD)

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Revision History

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Give Me Feedback!

Your comments on this project and suggestions for future hands-on research are welcome.

Brian Dipert
edndipert@worldnet.att.net
http://members.aol.com/bdipert
1864 52nd Street
Sacramento, CA 95819
Phone: 916-454-5242
Fax: 916-454-5101

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