September 24, 1998

EDN's 25th Annual Microprocessor/Microcontroller Directory

Motorola 68HC16
	View block diagram

Motorola's 68HC16 µC is a superset of and source-code-compatible with the 8-bit 68HC11; the HC16 has 261 instructions. The 68HC16 is an accumulator-based architecture; processing centers on two 16-bit accumulators. Three 16-bit index registers work with the accumulators. These index registers have 4-bit extensions for creating 20-bit addresses. Similarly, the stack pointer and program counter, both 16-bit registers, have 4-bit extensions, providing 20-bit address capability to a flat, 1-Mbyte memory map.

An integrated multiply-accumulate (MAC) unit comprises a 16-bit multiplicand register, a 16-bit multiplier register, a 36-bit accumulator, and two 8-bit-address mask registers. It performs a MAC cycle in 480 nsec at 25 MHz. The MAC unit uses a simplified form of modulo addressing to implement FIR filters and circular buffers.

Motorola built the 68HC16 modular architecture on the internal InterModule Bus (IMB), which simplifies the addition of on-chip peripherals. Bus protocols are based on the 68020 bus. The IMB contains circuitry to support exception processing, address-space partitioning, multiple interrupt levels, and vectored interrupts. The 68HC16 has a system-integration module that supports an external 20-bit address bus, a 16-bit data bus, and as many as 12 programmable chip selects. The module includes watchdog and periodic timers and a PLL that boosts a 32.76-kHz or 4.2-MHz crystal to system clock speeds as high as 25 MHz. You access memory-mapped, on-chip peripherals through dedicated peripheral registers.

The HC16 includes Motorola's in-circuit background-debugging mode (BDM), which allows read and write access of the target system's registers and memory and offers a set of debugging commands. You use BDM to program the on-chip flash and RAM. BDM lets debuggers do source-level debugging and monitor variables without using other processor resources, such as RAM or serial ports. Program and data share a common address or use two separate spaces. The 68HC16's addressing space expands to 1 Mbyte (2 Mbytes for separate code and data spaces for larger applications). Instruction boundaries are on even boundaries and use big-endian addressing. The CPU accesses words on word or byte boundaries.

Power management: Wait reduces current by stopping CPU execution while leaving the clock running. A low-power-stop (LPSTOP) instruction stops the clock.

Special instructions: The 68HC16 performs bit manipulation with instructions such as bit set, clear, and test. It also supports math instructions, such as add, subtract, BCD, decimal-adjust add, and signed and unsigned multiply and divide. A background operating mode uses special debugging instructions.

Development tools: The HC16 family has extensive development-tool support, including assemblers, compilers, emulators, debuggers, evaluation boards, and programmers from third-party vendors. (Visit www.mcu.motsps.com/dev_tools/ 3rd/index.html.)

Second sources: There are no second sources for the HC16 family.

Back to Microprocessor/Microcontroller Directory Main Page

| EDN Access | Feedback | Table of Contents |

Copyright © 1998 EDN Magazine, EDN Access. EDN is a registered trademark of Reed Properties Inc, used under license. EDN is published by Cahners Business Information, a unit of Reed Elsevier Inc.