September 24, 1998

EDN's 25th Annual Microprocessor/Microcontroller Directory

80186
	View block diagram

The register-based 80186 architecture is built on the 8086 core. The 80186 supports approximately 120 instructions and 14 16-bit registers, organized into four general-purpose, four pointer, four segment, and two special registers. The CPU addresses each general-purpose register as a 16-bit register or two 8-bit registers. The segment registers point to code, stack, and two local data segments.

The core architecture includes the processor-execution and the bus-interface units, which asynchronously communicate to the outside world via an 8- or a 16-bit multiplexed system bus. Some AMD 186s support a nonmultiplexed address/data bus, which frees the processor to run at nearly twice the speed of standard 80C186 controllers—without an increase in external-memory speed requirements. The unit uses a 6-byte instruction-prefetch queue to hold pending instructions fetched by the bus-interface unit.

All memory addressing is base-relative, which is a help for embedded code because you can easily change the address base to relocate code. Address segmentation lets the CPU address as much as 1 Mbyte of memory. The 80186 adds a 16-bit offset supporting a 64-kbyte segment to the segment base address (the segment register shifts 4 bits left) to attain a 20-bit address and 1 Mbyte of addressing capability. The CPU bus supports multiprocessing. The local-bus controller deploys a HOLD/HLDA (hold/hold-acknowledge) protocol that enables another bus master, typically DMA, to take over the common system bus.

Power management: Only the Intel versions of the 186 have idle and power-down power-saving modes. Idle shuts off the CPU clock, leaving all integrated peripherals active. Power-down disables the clock input. In addition, you can programmably divide the internal-processor frequency by a factor as high as 256 and slow all internal logic.

Special instructions: Math instructions include signed and unsigned multiply and divide, add, subtract, BCD, and decimal adjust. The 80x86 performs a register-exchange repeat prefix for repeating string operations (execute until zero or equal). Wait examines the test pin and suspends instruction execution if the pin is high.

Special on-chip peripherals: AMD's 186ER is the only 186 to support 32 kbytes of on-chip RAM. The 186ED integrates a DRAM controller. The new Am186CC integrates four channels of high-level data-link control (HDLC) and a Universal Serial Bus (USB) peripheral controller. Each HDLC channel has a maximum data rate of 10 Mbps. The USB interface is a 12-Mbps device controller with six endpoints and an integrated USB differential driver/receiver.

Development tools: The x86 architecture has more development tools than any other architecture. These tools include emulators, compilers, assemblers, simulators, debuggers, and more. AMD provides demonstration and evaluation kits for AMD-specific devices. The company also sponsors a third-party FusionE86 partner program, comprising a network of tool vendors that offer industry-standard x86 hardware and software.

Second sources: AMD and Intel are the primary suppliers of 186 devices. NEC (www.nec.com) and Vadem (www.vadem.com) make code-compatible µPs and µCs.) Harris Semiconductor (www.harris.com) is the second source for the 8086 and 80286.

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