September 24, 1998

EDN's 25th Annual Microprocessor/Microcontroller Directory

Intel MCS-96/296
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The MCS-96 microcontroller product family comprises the event-processor array (EPA), the high-speed I/O (HSIO), and the motion-control (MC) lines. The EPA line comprises the KR, NT, NP, and NU devices. The HSIO line consists of the KB, KC, and KD devices. The MC line, which comprises the MC, MD, and MH devices, supports motor-control applications.

Intel's MCS-296 microcontroller is the most recent addition to the 196 family. The 80296SA improves performance over the 8xC196NP and 8xC196NU controllers and maintains binary-code compatibility. You can drop it into an 8xC196NP/NU socket. The 80296SA exhibits improved math performance over previous architectures, making it suitable for embedded digital-signal processing and feedback-control systems. The 80296SA uses the same peripherals as the 8xC196NP/NU.

Intel built the MCS-96 around 256 RAM-based registers; most of the registers can function as a result accumulator. The first 23 of these registers are special-function registers to control the on-chip peripherals. Some family members have on-chip RAM that can hold small, critical dynamic code or data and can implement register windowing. Register windowing can substitute a block in RAM for a block of registers. The MCS-96 maps accesses to a register in the window block to the windowed block in RAM. This technique eases fast context switches by shifting the register window to another block. Block sizes can be programmed for 32, 64, or 128 bytes.

The MCS-96 has approximately 220 instructions comprising one, two, or three operands. Some instructions are more than one word. Register windowing helps minimize instruction size by letting 8 bits address a register in a movable window.

The address space of the MCS-96 works with both 8- and 16-bit external data buses. The external bus multiplexes data and address lines, so a buffer must hold the address stable during data transfers. However, the 8xC196NP has a demultiplexed external bus. An on-chip memory controller lets the MCS-96 use a range of memory types and speeds. External-memory wait states are programmable. Most 96/296 devices can access as much as 64 kbytes of memory; some versions can extend this memory range to 16 Mbytes.

The CPU can use autoprogramming to program the internal EPROM with an 8-bit external data interface. All MCS-96 chips except the Mx have a full-duplex serial port, which the 196Kx uses to program the µC.

Power management: Idle mode shuts off the CPU clock, leaving all integrated peripherals active. Power-down mode disables the clock input.

Special instructions: Math instructions include add, subtract, multiply, divide, and multiply-accumulate. Special instructions include a block move of data; indirect-autoincrement addressing; and a table-indexed jump, which lets you jump via a table value.

Special on-chip peripherals: The MCS-196's EPA contains two 16-bit timers and 10 capture-and-compare modules. An event interrupt generates edges, starts A/D conversions, and resets timers. The HSIO structure has as many as four input and six output timer/counter-driven lines. The 196 also supports a peripheral-transaction server that is a microcoded, hardware-interrupt handler for responding to data transfers, starting an A/D conversion, and performing similar tasks.

The 8xC196 bus controller features programmable wait-state generation, 8- or 16-bit bus width, and support for a HOLD/HLDA (hold/hold-acknowledge) protocol for multiprocessor systems. The 8xC196NP and NU have a dynamically selectable multiplexed/demultiplexed bus and a chip-select unit.

The 8xC196NU and 80296SA include a PLL. With the PLL, an external clock drives the device at one-half or one-fourth the maximum internal clock frequency. Therefore, a 196/296 system supports a lower frequency external clock or oscillators while maintaining the maximum internal operating frequency. The 296's chip-select unit allows you to window some external-memory locations for direct addressing, an improvement over the 196.

Development tools: Intel and many third-party vendors provide tools for the 196 and 296. Intel's evaluation boards provide a low-cost hardware platform for code execution, debugging, and performance analysis. You can configure a board's memory (ROMsim) to closely match the performance and structure of your planned memory configuration. All evaluation boards come with a ROM monitor that can communicate with 196 development-tool debuggers or with a serial interface. Using development tools, you can download 196 object files from the program counter to execute and debug code on the board. You can then use the evaluation board with your application software as part of your prototype-hardware design. The address-bus and data-bus; I/O-port; and other necessary device pins, including reset, power, and ground, are available through headers on each board. You can connect prototype hardware to these pins and operate the board in a stand-alone mode to evaluate the system design.

Intel's assembler package comprises a macroassembler, a linker/locator, utilities, and a Windows-based embedded development environment. The linker/locator creates an absolute or executable load image. (Refer to http://developer.intel.com/design/mcs96/index.htm for more information.)

Second sources: There are no second sources for the Intel MCS-96/296.

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