September 24, 1998

EDN's 25th Annual Microprocessor/Microcontroller Directory

Siemens SABC16x
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Operations within Siemens 166/165/167 µCs center on 16-bit registers in as many as 16 banks, as well as on a 16-bit program counter and a 16-bit program-status word. The dual-ported RAM banks let the CPU read a register for the next operation while writing back the results of the current operation to another register. On-chip peripherals work independently of the CPU with a separate clock generator. The CPU and peripherals interchange data and control information via special-function registers.

The main core of the CPU comprises a four-stage pipeline: fetch, decode, execute, and write back; a one-cycle barrel shifter; and a fast-multiply/divide-function unit. Pipeline stages clock in 100-nsec cycles, so most of the µC's 240 instructions appear to execute in one cycle. Instruction latency is four cycles, or 400 nsec. A peripheral-event controller performs byte or word transfers between peripherals and memory in one cycle without interrupting the CPU. The CPU uses code segmentation and data paging to address as many as 256 kbytes (the 166) or 16 Mbytes (165/167) of the unified instruction-data memory space. The external-memory bus controller has four programmable modes, chip selects, and a wait-state generator. You can partition physical memory into multiple segments and five address ranges (the 166 has only two), each having a different type of memory with or without wait states. You can program a hold/acknowledge mechanism on the external bus so that external devices take control for critical data transfers. A system stack of as much as 512 bytes stores temporary data.

Instructions are 2 or 4 bytes long. The µCs can handle a 4-byte instruction fetch from on-chip ROM in one 100-nsec stage. A single fetch gets an entire instruction. However, because the 16-bit external bus permits only a single-word access, off-chip program accesses suffer at least a one-cycle stall for a 4-byte instruction.

The 166/165/167 µCs cache branch-target instructions and use them to supply the next iteration of a branch, allowing execution without pipeline stalls. First-pass loop branches pay a single-cycle penalty. Nonaligned, double-word, branch-target instructions also pay a one-cycle penalty.

Power management: Idle mode shuts off the CPU clock, leaving all integrated peripherals active. Power-down mode disables the clock input. Any reset or interrupt request can terminate idle mode; only a hardware reset can terminate power-down.

Special instructions: Bit-manipulation instructions include bit set, clear, move, and various logical operations. Math instructions are add, subtract, 16X16-bit multiply and divide, and 32X16-bit divide. The µCs can perform as many as 15 shifts or rotates in one instruction cycle. Every jump has 16 conditions.

Development tools: The list of third-party support for the 166 is too extensive, so check out www.directories.mfi.com/ embedded/siemens/. In addition, Siemens has developed a CD-ROM-hosted digital application engineer (DAvE) that helps you program the C166 by offering wizards to configure the chip and automatically generate C-level templates with appropriate driver functions for all on-chip peripherals and interrupt controls. The company also has a useful Web site at www.spacetools.com (SiemensPartners for Applications using Chips for Embedded control) for finding application-oriented support.

Second sources: The ST10 devices from STMicroelectronics are 166-compatible.

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