September 24, 1998

WHAT'S HOT IN THE DESIGN COMMUNITY

Precision op amp shrugs off problem of Y2K—and beyond

Analog components are inherently immune to the pervasive millennium software bug (so there!), but their stability is subject to the drift impact of time and temperature. Countering this drawback, National's LMC2001 guarantees key performance parameters over 10 years, most notably with less-than-5-µV long-term offset-error drift. National doesn't ignore short-term variation, either: The op amp, for strain gauges, weigh scales, and monitoring equipment, homes in on an offset voltage of less than 40 µV within 15 msec of power-up. Temperature performance is similarly stable with typical offset drift less than 0.015 µV/°C.

An innovative architecture and internal signal-processing technique for this IC results in no 1/f input-voltage noise—a frustrating source of error in low-bandwidth transducer circuitry. The LMC2001's 6-MHz gain-bandwidth product, 5V/µsec slew rate, and 250-nsec settling time to 1% make this op amp suitable for wideband designs. CMRR and power-supply rejection ratio are greater than 120 dB. Overall op-amp performance is superior to that of chopper-stabilized devices but without their noise, recovery, and power drawbacks.

The 5V rail-to-rail device requires a quiescent current of 750 µA and costs $1.20 (1000). It is available in eight-lead SOIC and SOT23-5 packages. Both packages use an all-copper lead frame instead of the conventional Kovar frame to eliminate the small but significant thermocouple effect that occurs between dissimilar package-to-circuit-board metals at even a small temperature differential.

—by Bill Schweber

National Semiconductor Corp, Santa Clara, CA. 1-800-272-9959, www.national.com/pf/LM/LMC2001.html.

Riser-card standard complements AC'97

When Intel published the AC'97 Revision 2.1 standard this spring, it was evident that a piece was missing: The 2.1 Revision finalized an architecture for a combined audio and modem subsystem in PCs yet lacked a mechanical standard for a card to host the needed connectors and, potentially, the analog ICs (see "Divide and conquer: AC'97's sound strategy for multimedia PCs," EDN, July 16, 1998, pg 50). Now, Intel has added the Audio/Modem Riser (AMR) specification for desktop PCs and the Mobile Daughter Card (MDC) specification for notebooks. AMR and MDC cards will use the AC-Link interface and allow OEMs a number of options for modem and audio implementations. Expect immediate support for AMR from companies such as Rockwell (www.rss.rockwell.com) and ESS Technology (www.esstech.com) that offer modem, audio, and AC'97 technology. You can download the AMR and AC'97 specs at http://developer. intel.com/pc-supp/ac97.

—by Maury Wright

Dual drivers, receivers help LVDS punch through interface challenges

Physical-interface datacomm-component vendors (a fancy way of saying "analog suppliers") are adding to their portfolios of ICs supporting low-voltage differential-signaling (LVDS), which offers greater distances, lower power and EMI, and better noise immunity than do other signaling formats. The Texas Instruments SN65LVDS050 and the SN65LVDS051 driver/receiver devices (figure), which differ only in their driver/receiver-enabling structures, extends the company's LVDS family.

The ICs operate from a single-ended 3.3V supply and tolerate as much as 5V on their I/O pins. Propagation delay for the drivers is less than 2.5 nsec; receivers offer open-circuit fail-safe mode, so noise does not appear as a valid signal in your system. Equally critical is their ESD protection of more than 8 kV on the bus pin. These LVDS ICs come in 16-pin SOICs and cost $3.73 (1000).

—by Bill Schweber

Texas Instruments Inc, Dallas, TX. 1-800-477-8924, www.ti.com.

Processor family is "QUICC" to include high integration

The most popular PowerPC device family to date is probably Motorola's MPC860 PowerQUICC series for networking and telecommunications equipment. So, it's no surprise that Motorola has developed a higher performance successor, the MPC8260 PowerQUICC II (figure), that can process data as fast as 710 Mbps. The MPC860 and MPC8260 series devices integrate many of the same peripherals. Both series contain a core processor that performs general supervisory functions and software-driven protocol processing and a separate communication-processor module (CPM) that is dedicated to processing communication protocols. The CPMs also handle serial-channel interrupts and perform hard-wired protocol-processing functions. But significant differences exist between the two series.

For starters, the MPC860's core runs at only 66 MHz compared with the 100- to 200-MHz MPC8260's EC603e core. The MPC860 core contains only 4-kbyte instruction and data caches and 5 kbytes of dual-ported RAM, whereas the MPC8260 contains 16-kbyte, four-way set-associative caches and 24 kbytes of dual-ported RAM for protocol parameters.

The MPC8260's low-power EC603e is a 32-bit, multi-issue core. It has a 64-bit interface allowing it to pipeline two 32-bit instructions for execution. This interface also allows the processor to move data around in 64-bit chunks, increasing data-handling efficiency.

The MPC8260's CPM is an independent, 133- or 166-MHz RISC microcontroller that supports four simultaneous multiple-communication protocols, including as many as three 10/100-Mbps Ethernet protocols and two 155-Mbps ATMF user-network interface 4.0-compliant ATM segmentation-and-reassembly protocols. The CPM also incorporates two multichannel communication controllers (MCCs) supporting multichannel HDLC transmission. Each MCC can handle as many as 128 full-duplex serial channels for a total of 256 64-kbps channels. Two time-slot assigners enable you to multiplex these channels on as many as eight time-division-multiplexed (TDM) ports; the MCCs can therefore support as many as eight T1 lines. The CPM also supports four SCCs, two SMCs, SPI, and I²C.

The PowerQUICC II contains a system-interface unit (SIU) for system-control and glue-logic functions, including a memory controller. The memory controller supports as many as 12 memory banks of SRAM, EPROM, EEPROM, flash, and most DRAMs. It has three user-programmable state machines; a general-purpose chip-select state machine; and a page-mode, pipelined-SDRAM machine. The SIU also supports a 64-bit data bus, a 32-bit PowerPC address bus, and a 32-bit PCI bus. The PCI bus provides a direct path for the CPM to access memory and supports the Intelligent I/O controller (I²0) message-passing protocol.

PLX Technology (www.plxtech.com) supports the MPC8260 with the $49 (100), 64-bit, 66-MHz PCI 9610 FlexPort chip. The chip handles a variety of data widths and speeds and provides a platform for scalable migration of 32-bit PCI- and local-bus designs to 64 bits and 66 MHz. The PCI 9610 implements the PLX's FlexPort feature set, an extension of PLX's Data Pipe Architecture technology. FlexPort enhances the Data Pipe Architecture technology with the Memory Fat Pipe, enabling designs based on 32-bit processors to achieve 64-bit performance as fast as 528 Mbytes/sec, and the Adaptive FIFO Architecture, boosting the burst-transfer performance of any PCI application.

For development support, Motorola offers a PowerQUICC II tool kit that comprises schematics, initialization code, and drivers. You can find a list of third-party development tools at motorola.com/mpc8260/third_pty_tools. The first device from this family runs at 133 MHz (core and CPM) and 2V. It comes in a 480 TBGA package and sells for $105 (10,000).

—by Markus Levy

Motorola, Austin, TX. 1-512-895-6082. www.mot.com/mpc8260.

Formal-verification tools boast enhanced design debugging

Verplex has introduced two new formal-verification tools: the Tuxedo-LEC logic-equivalence checker and Tuxedo-LDD logic-debugging and diagnostic tool. LEC includes RTL extraction, letting you compare designs before and after logic synthesis. You then continue to use the tool to compare designs before and after gate-level modifications, such as adding design-for-test features, and after placement-and-routing with a circuit-extraction tool. According to Verplex, LEC's correlation-learning and key-point-mapping capabilities speed design verification and reduce platform-memory requirements. The tool does key-point mapping by functional relationship examination, even on versions with different design hierarchies. This type of mapping reduces the chance of false errors that can occur when a verification tool uses naming conventions to compare two versions of a design. Another important LEC feature is the tool's ability to deal with "don't-care" cases, particularly useful for RTL and gate comparisons, to reduce false errors.

Tuxedo-LDD identifies and displays error candidates (differences between two versions of a design). You can place constraints on the comparison to eliminate known differences that the tool should not flag. When it detects differences, the tool highlights those differences on a schematic window for graphical debugging, along with a textual listing of mapped and compared points.

The Tuxedo-LEC equivalence checker and Tuxedo-LDD debugging and diagnostic tool cost $80,000 and $25,000, respectively. Verplex sells LDD as a separate tool, letting you buy additional equivalence checkers without the expense of unwanted debugging-tool copies. The tools now work on Verilog, and VHDL capability will come in the first quarter of 1999.

—by Jim Lipman

Verplex Systems, Santa Clara, CA. 1-408-980-8300, fax 408-980-8215, www.verplex.com.

Instrumentation amp grapples with precision, ruggedness conundrum

Front-end amplifiers for transducers in industrial and instrumentation applications face conflicting goals of providing accuracy while resisting those inevitable input faults and ESD spikes. The LT1167 from Linear Technology (figure) stares down this problem by combining dc precision with fault protection. With 20-kOhm external input resistors, the instrumentation amp protects against faults to ±400V dc and ESD spikes greater than 4 kV, meeting IEC 1004-2 Level 2 ESD requirements.

You set the gain of this instrumentation amp from 1 to 10,000 with an external resistor. At gains of 1 to 10, the inherent gain error is less than 0.05%, so your resistor's tolerance is the major source of gain error; at gain of 10, maximum gain error is 0.04% maximum. Gain nonlinearity at this same nominal value is 10 ppm, and maximum input-offset voltage is 40 µV. With bias current of less than 350 pA and offset current of less than 320 pA, the offset-induced voltage error for this amp is 6.4 µV with 20-kOhm input resistors. At 1 kHz, its voltage noise is 7.5 nV/[sqr root]Hz. The eight-pin SOIC operates from ±2.3 to ±18V with 0.9-mA typical quiescent current and is specified for -40 to +85°C operation. It costs $3.20 (1000).

—by Bill Schweber

Linear Technology Corp, Milpitas, CA. 1-408-432-1900, fax 1-408-434-6441, www.linear-tech.com.

Miniature hard drive stores 340 Mbytes

Based on a CompactFlash Type II form factor, IBM's new microdrives can store 340 Mbytes on a quarter-sized media.

After years of rumors, IBM has finally announced a 1-in. disk drive. Using one disk platter the size of a quarter, the drives will debut with one or two heads and storage capacities of 170 and 340 Mbytes. IBM calls the units "microdrives" and believes the peripherals will enable new classes of small, portable, consumer-electronics devices. The company designed the drives for rugged applications that require removable media. The design target was a drive that can withstand 1000g shock and operate from AA batteries. The microdrives use the CompactFlash Type II (www.compactflash.org), 42.8X36.4X5-mm mechanical form factor that relies electrically on the ATA interface. Devices such as digital cameras, handheld computers, personal digital assistants, and printers sport CompactFlash slots, and IBM lists these products as key target markets. IBM has yet to set prices for the drives but claims the units will feature lower cost per megabyte than flash-based CompactFlash cards. Currently, such flash-based cards top out at 60 Mbytes and sell for around $200 in high volumes. IBM will make the microdrives available for sampling this year and targets mid-1999 for production volumes.

It will be interesting to see whether IBM can succeed where Hewlett-Packard (www.hp.com) failed years ago with the 1.3-in. Kitty Hawk. In IBM's favor, evolving disk-recording densities have made reasonably high capacities feasible. Unlike HP, IBM has chosen to internally manufacture the microdrives using technology such as giant magnetoresistive heads gleaned from its 21/2-in. products. HP chose to partner with Citizen Watch Co on the Kitty Hawk project because of Citizen's expertise in manufacturing miniature devices. The partnership seemed to work well, although the technology failed because of inadequate storage capacities. IBM admits to adding some new technologies, such as head loaders, in the microdrives but believes it can scale its assembly techniques to build the drives in volume.

—by Maury Wright

IBM, San Jose, CA. 1-416-383-5161, www.ibm.com/storage/microdrive.

LAN-switch ICs distribute intelligence

Enterprise LANs have quickly moved to switch-based technologies to maximize bandwidth. In turn, semiconductor vendors have rolled out an array of switching ICs for hubs, switches, and routers. MMC Networks is now taking the next logical step: moving switching intelligence closer to the LAN ports and making the ICs programmable so that manufacturers can update equipment to match the constant parade of new network standards for multimedia, quality of service, security, and Internet support.

Most LAN switches combine a RISC processor and either off-the-shelf or ASIC switch ICs. MMC reverses the architecture somewhat. The core of the company's new AnyFlow offering for wiring-closet switches is the nP5400 switch-fabric IC. It performs wire-speed switching with an aggregate bandwidth of 20 Gbps. A single 5400 IC can support 24 Fast Ethernet ports and 2 Gigabit Ethernet ports or a variety of other combinations. Moreover, you can gang four of the ICs using the company's ViX time-division-multiplexed (TDM) bus.

To feed the 5400 via the ViX bus, MMC offers four-channel Ethernet-port-interface (EPIF) ICs with integrated media-access controllers (MACs). The ICs integrate a custom microcontroller to process packets performing wire-speed address translation. Moving the intelligence near the MACs promotes scalable designs that can maintain wire-speed capability as the number of ports grows. Moreover, the programmability lengthens product life because it lets you add features as standards emerge. MMC claims that the OEM cost of the architecture will be less than $200 per port. The company also plan ViX-based front ends for the 5400 that support other networks, such as asynchronous-transfer-mode systems.

—by Maury Wright

MMC Networks, Sunnyvale, CA. 1-408-731-1600, www.mmcnet.com.

PCI and CompactPCI boards sport "ultimate" ADC

PCI and CompactPCI data-acquisition boards that National Instruments (NI) expects to introduce late this year or early in 1999 will feature a unique ADC. The circuit brings the test-and-measurement industry several steps closer to the long-sought-after (and unachievable) "perfect" ADC. Using a technology that, pending a trademark search, NI tentatively calls the "Flex ADC," the converter achieves a spurious-free dynamic range (SFDR) of 26 bits (equivalent to approximately eight decimal digits) at 10,000 conversions/sec. Moreover, as you reduce the signal level, the unit maintains its SFDR, even with signals that represent a small fraction of full scale. Because its architecture is an elaboration on delta-sigma technology, the ADC can also take 100 million samples/sec with 8-bit resolution. As you decrease the conversion rate to less than about 15 million samples/ sec, the resolution increases. At 5 million samples/sec, for example, resolution is 16 bits.

In using an 8-bit flash ADC as a delta-sigma converter's basic encoder, NI's converter is unusual. Most delta-sigma ADCs use a 1-bit encoder. Although delta-sigma ADCs that use multibit encoders can be faster than those that use 1-bit encoders, the speed comes at a price. The multibit encoders exhibit linearity errors that can spoil the delta-sigma device's linearity. The idea of measuring and mathematically correcting for the linearity errors of a multibit encoder in a delta-sigma ADC dates back to 1989. Still, NI's vice president of engineering, Carsten Thomsen, believes that NI's development of a practical method of performing the corrections is a first. The US Patent Office agrees; it has granted NI three patents on the Flex ADC, and the company has applied for six more.

The correction scheme makes clear the designers' roots in precision audio measurements. Thomsen and several key members of the Flex ADC design team spent many years working for Danish audio-measurement company Bruel and Kjaer before they joined NI. The correction scheme uses an ultra-low-distortion sine-wave oscillator. When you first apply power to the ADC, the flash converter encodes the oscillator output. Because the waveform is a sine wave, its characteristics are fully known. The Flex ADC circuitry can thus accurately characterize the flash encoder's departures from perfect linearity. Several FPGAs (in effect, custom DSPs that, together, perform 6 billion operations per sec) then apply the corrections on the fly.

The converter operates within an environment whose temperature is maintained within 2°C. However, if the external ambient temperature changes by more than 5°C from the temperature at power-up, NI advises recalibration. When the ADC operates as a flash converter, you can trigger it in a conventional manner. In delta-sigma mode, the converter makes continuous conversions. However, by stopping the conversions when you detect an anomalous signal condition, you can capture a history of how the signal behaved before the anomalous conditions. The onboard memory stores 16 Mbytes, the equivalent of 4 million samples when the converter is delivering its highest resolution.

NI has built more than 20 PC-based instruments by teaming the Flex ADC with an elegant frequency-synthesized arbitrary-waveform-generator board and appropriate virtual-instrument software. NI had not set a firm price by press time but expects the ADC boards to cost less than $10,000—probably by a significant amount. Beta versions will be on their way to selected system integrators within a month.

—by Dan Strassberg

National Instruments, Austin, TX. 1-800-258-7022, fax 1-512-683-8411, www.natinst.com.

Cadence acquires Lucent's EDA group

Cadence plans to buy the EDA arm of Lucent Technologies, the Bell Labs Design Automation (BLDA) group. With the acquisition, Cadence picks up more than 100 BLDA employees and a number of EDA tools, including the FormalCheck model checker, Clover physical-verification tool suite, Attsim mixed-mode simulator, and Celerity transistor-level simulator. Cadence plans to employ FormalCheck to complement the company's Affirma formal equivalence checker, announced this summer. The company will evaluate the other BLDA tools to determine their applicability within Cadence's EDA product offerings.

The agreement between both companies also includes a three-year agreement by Cadence to support Lucent's EDA requirements. Cadence's Berkeley Labs and Bell Labs' research group will also work on chip-verification and other EDA tools and methodologies for future chip-design requirements.

—by Jim Lipman

Cadence Design Systems, San Jose, CA. 1-408-943-1234, fax 1-408-943-0513, www.cadence.com.

Bell Labs Design Automation, Murray Hill, NJ. 1-800-875-6590, fax 1-908-582-5145, www.bell-labs.org/blda.

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