September 24, 1998

EDN's 25th Annual Microprocessor/Microcontroller Directory

Motorola 680x0
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Motorola built the 680x0 architecture around 16 general registers with a 68000-compatible, orthogonal instruction set. The 680x0 has more registers than the original 68000. Motorola added the control registers to control the memory-management unit (MMU) and the floating-point unit (FPU) and to support additional processing capabilities. For example, the 68040 adds eight 80-bit floating-point registers and 12 control registers.These registers include a vector-base register, points to an interrupt-vector table; a cache-control register; user and supervisor root pointers; and translation registers.

The superscalar 68060 heads the 680x0 line-up with its dual integer and floating-point pipelines. As instructions enter the CPU, they flow into a four-stage prefetch pipeline: instruction-address generation, instruction cycle, instruction early decode, and instruction buffer. In this pipeline, the 680x0 converts 68000-compatible, variable-length CISC instructions to a fixed-length instruction. These instructions then enter dual, four-stage, synchronously operating, integer-execution pipelines. The decode, effective-address-calculation, fetch, and integer-execution pipeline dispatches instructions to the FPU and allows for some execution overlap between the integer and FPU engines.

A Harvard architecture allows the 68060 to perform simultaneous instruction fetches and data accesses. The four-way set-associative, four-way-interleaving, on-chip caches support simultaneous read and write operations. You can freeze portions of the caches to prevent reallocation.

The 68040 implements a fetch, decode, effective-address-calculation, effective-address-fetch, execute, and write-back pipeline. To speed processing, the device has two 4-kbyte direct-mapped caches and separate data and instruction MMUs, which allow simultaneous address translations. The 040 includes bus snooping to ensure cache coherency for multiprocessing. The cache supports both write-through and copy-back modes. The 68020 and 68030 CISC implementations have smaller caches; the 030 and 040 versions implement burst mode, moving as much as 16 bytes in an addressing block between registers and memory.

The 040 and 060 deliver apparent single-cycle execution for some instructions, mainly register operations such as memory-to-register moves if the data is in the data cache. A taken branch takes two cycles; a not-taken branch takes three cycles. On the 68060, a 256-entry, four-way, set-associative, on-chip branch cache allows taken and nontaken branches to execute in zero and one clock, respectively. The branch-cache unit contains state bits that provide a history of branch executions, which helps to predict branch direction.

Unlike the 020/030, the 040 and 060 perform no dynamic bus sizing. Instead, they have a highly reliable bus with a high-drive option that can implement a synchronous, two-clock read/write protocol. A 4-word burst takes five clocks. The 040 includes multiprocessor-bus arbitration but requires off-chip logic. Externally, the 68060 bus is a superset of the 68040 bus. Additional signals support higher performance system designs, but the processor can easily operate on a 68040-based bus. An on-chip MMU with separate instruction and data translation-look-aside buffers allows the 68060 to access as much as 4 Gbytes of memory.

Power management: To support power management, the 68060's functional units respond to dynamically controlled clocking; the caches and execution units power down when not accessed. The static design allows you to reduce or stop the external clock, and a low-power-stop (LPSTOP) instruction disconnects most of the chip from the clock pin.

Special instructions: The CPUs have special instructions for variable-length bit fields; moving 16 registers; compare; and swap, which locks memory for multiprocessing. A scaling option addresses data by item size for table-access, FPU, and MMU commands.

The 68040 and 68060 have a special move instruction (MOVE16) to perform a 16-byte block move and a PLPA instruction that loads a physical address by translating a logical address. A table instruction performs a table look-up and interpolates the data.

Special peripherals: The MC68150 allows the 68040, LC040, and EC040 bus to communicate bidirectionally with 32-, 16-, or 8-bit peripherals and memories. The XC68HC901 multifunction peripheral comprises a one-channel USART and an eight-source interrupt controller.

Development tools: The 680x0 shares many of the same tools as the 68EC000.

Second sources: Toshiba acts as a second source for some versions of the 680x0.

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