September 24, 1998

EDN's 25th Annual Microprocessor/Microcontroller Directory

ARM processors
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ARM designs µP cores and cached macrocells for its licensees. Partners offering ASICs with embedded ARM cores are Atmel/ES2, Cirrus Logic, Mitel, IBM, LG Semicon (www.lgsemicon.co.kr/), LSI Logic, Lucent (www.lucent.com), National Semiconductor, NEC, Oki, Samsung, Seiko Epson (www.epson.co.jp/), Sharp, Symbios Logic (www.symbios.com), TI, and VLSI. Some partners offer the ARM core in embedded products for vertical markets.

ARM processors comprise the ARM7 Thumb, ARM9 Thumb, and StrongARM product families. (ARM will announce ARM10 in October.) All the processors support the ARM instruction set, providing full software compatibility over a range of performance and cost.

The ARM cores and cached macrocells implement a load/store architecture and have 31 general-purpose registers with 16 simultaneously visible. A fast interrupt has a minimum latency of four processor cycles and uses seven private registers to minimize state-saving overhead. All registers, excluding the program counter, are general-purpose, although a set of conventions, the ARM Procedure Call Standard, governs the registers' use for C compatibility.

The ARM cores and cached macrocells support user and supervisor modes for controlling access; they handle interrupt-request, fast-interrupt-request, abort, and undefined exception-processing modes. Modes use register windows to overlay some of the 16 general-purpose registers.

The Thumb architectural extension is primarily a 16-bit subset of the 32-bit instruction set. On execution, the Thumb module, residing within the instruction pipeline, decompresses the 16-bit instructions back to 32-bit instructions without added delay. The Thumb module adds about 6% to the core's die size but helps increase code density and overcome the waste from using 32-bit fixed-length instructions.

The bus clock for most ARM cached macrocells can be synchronous or asynchronous with respect to the internal cache clock. All ARM cached macrocells contain a write buffer, which lets execution continue while writes are pending. The buffer holds 8 words at four independent addresses.

The ARM7 Thumb family comprises the ARM7TDMI core and ARM7x0T cached macrocells. This architecture, Version 4T, consists of a three-stage—fetch, decode, and execute— pipeline to achieve single-cycle instruction execution. All cores use an 8-bit Booth multiplier, which executes in five or fewer cycles for 32X32-bit multiply and offers 64-bit multiplication. The ARM740T integrates a simplified memory-management unit (MMU) that allows you to specify eight memory areas by individually programming their base address, size, cache control, write-buffer control, and access permissions. This approach simplifies the programmer model and reduces the core size to less than that of the ARM710T and ARM720T.

ARM based the ARM9 Thumb family, available as the ARM940T, on the ARM9TDMI core. The core is also an implementation of the ARM Version 4T architecture but with a five-stage—fetch, decode, execute, memory, and write-back—pipeline. The additional pipeline depth and design implementation double the performance over the ARM7 Thumb cores. The bus architecture also differs, using a Harvard approach compared with the ARM7 Thumb core's von Neumann architecture. The ARM940T implements the same MMU as the ARM740T. You can use the cache in write-through and -back modes; write-back mode reduces the number of external transactions from the core.

StrongARM uses a five-stage pipeline and Harvard architecture and supports Version 4 of the ARM architecture. It provides a fourfold increase in performance over the ARM7 Thumb cores. Intel now produces and develops StrongARM, which is available as the standard SA-110 processor and as part of custom logic products.

The cores avoid excess pipeline flushes—Strong-ARM by using early branch execution and ARM7 by using static branch prediction, always taking the rear branch as in a loop. The SA-110 has separate instruction and data MMUs. The translation-look-aside buffers (TLBs) have 32 entries that can each map a segment, large page, or small page and use a round-robin replacement algorithm. The data TLB supports both flush-all and flush-single-entry functions, and the instruction TLB supports only the flush-all function.

Power management: All the ARM processor cores and cached macrocells are static designs. Furthermore, the designs use gated clocks and transparent latches, clocking the logic only during an operation (but not during a wait state).

Special instructions: ARM has 11 basic types of fixed-length instructions, which execute conditionally—not just branch—and reduce the need for short pipeline-flushing branches. A not-taken instruction executes in one cycle. Taken branches incur a three-cycle delay. The 16 execution-condition codes include equal, not equal, always, negative, and overflow. The ARM lacks explicit shift instructions; instead, all ALU operations can perform an optional shift operation in one execution cycle. The processors have block-data-transfer instructions to load and store data from any subset of the 16 general-purpose registers.

ARM processors lack an integer-divide instruction; however, the chips have multiply and multiply-accumulate (MAC) instructions. The MAC instruction speeds math-intensive applications. ARM processors can synthesize division and multiplication by a constant using sequences of one or more shift-and-add or shift-and-subtract instructions. (For example, division by 4 and multiplication by 5 each take one cycle.)

Special on-chip peripherals: The ARM7 Thumb and ARM9 Thumb processor cores have integrated EmbeddedICE logic, allowing you to debug the core via a JTAG interface. The ARM Advanced Microcontroller Bus Architecture (AMBA) interface is the standard bus interface to ARM7 Thumb and ARM9 Thumb cached macrocells.

Development tools: ARM offers a variety of software-development tools and hardware-development platforms, including the ARMUlator instruction-set emulator. A range of third-party development tools and operating systems also support the ARM architecture. Cygnus Solutions (www.cygnus.com), Embedded Performance (www.episupport.com), Green Hills Software (www.ghs.com), Metaware (www.metaware.com), Microtec (www.microtec.com), Microware Systems Corp (www.microware.com), and Wind River (www.windriver.com) offer development-tool chains and compilers. Accelerated Technology (www.atinucleus.com), Chorus Systems (www.sun.com), CMX Co (www.cmx.com), Embedded Performance, Etnoteam (www.etnoteam.it/), Geoworks (www.geoworks.com), Integrated Systems (www.isi.com), Microsoft (www.microsoft.com), Microware, Psion Software (www.psion.com), US Software (www.uss.com), and Wind River provide RTOS support. Hewlett-Packard (www.hp.com), Lauterbach (www.lauterbach.com), and Yokogawa Digital Corp (www.yokogawa.com) offer a debugger and an in-circuit emulator.

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