September 24, 1998

EDN's 25th Annual Microprocessor/Microcontroller Directory

Motorola ColdFire
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Motorola's ColdFire, or VL-RISC (variable-length RISC), architecture evolved from the M68000. VL instructions help to attain higher code density. Also, the ColdFire architecture eliminates M68000 instructions, which embedded applications rarely use, and optimizes the pipeline. As a result, it has fewer transistors—approximately 55,000—than the M68000. ColdFire continues to use the M68000 programmer's model.

Motorola designed three versions of ColdFire. The first version was relatively short-lived. The version 2 and 3 architectures comprise two decoupled subpipelines: an instruction-fetch pipeline (IFP) and an operand-execution pipeline (OEP). An instruction buffer separates the two pipelines and minimizes pipeline stalls. Motorola's design goals for V2 included making the core as small as possible. Hence, V2's IFP is a simple two-stage pipeline: instruction-address generation and instruction fetch.

Design goals for V3 were to stretch the pipeline to allow the device to operate at clock frequencies of 90 MHz and higher. For starters, the V3 core includes multiple clock domains that allow it to operate at a higher frequency than the remainder of the µP. V3's IFP includes two additional stages to help pipeline the address-generation and instruction-fetch phases. One of the additional stages is an instruction early decode to help reduce decoding time. This concept, borrowed from the 68060, includes some branch-acceleration techniques. For example, the early-decode mechanism considers that backward branches are taken. By default, the mechanism considers forward branches taken, but a condition-code register bit allows you to set up forward branches to be not taken.

In the V2 implementation, the instruction buffer comprises a three-long-word-entry FIFO buffer. The V3 implementation holds three complete instructions, regardless of length. This instruction buffer essentially converts variable- into fixed-length instructions.

A modular, standard bus architecture separates the CPU core from on-chip peripherals. The core communicates with on-chip memories using the tightly coupled Kbus processor. This bus lets the core perform a 32-bit fetch from internal memory in one clock cycle by pipelining the address and data. A controller interface on the Kbus indirectly attaches the core to user-selectable cache, ROM, and RAM modules. V3 uses a two-stage, but pipelined, Kbus that adds one cycle to most operand-read accesses; however, the increased operating frequency offsets the extra cycle. Another bus, the Mbus (master bus), offers centralized arbitration. A special module connects the Mbus to the Kbus. The Sbus (slave bus) interfaces to standard on- and off-chip peripherals and attaches to the Mbus through a system-bus controller.

On-chip debugging supports real-time trace; real-time and non-real-time debugging; and access to control registers to define types of memory regions, such as cacheable copy-back, write-through, and noncacheable. Real-time trace reflects the processor's status and indicates events such as instruction completion and monitoring change-of-flow target addresses. Real-time debugging supports program-counter-relative, operand-address, operand-data, and non-real-time-debugging hardware breakpoints. Non-real-time debugging is similar to background-debugging mode on current 683xx products. You can use a three-pin serial interface in this mode to read register contents, generate an infinite-priority interrupt, and force the CPU to halt.

Power management: A low-power-stop (LPSTOP) instruction shuts down active circuits in the processor and halts instruction execution. Processing resumes via a reset or valid interrupt.

Special instructions: ColdFire added 32X32-bit integer-multiply, register-sign-extension, and multiword nonoperation instructions to the 68000 architecture. Compilers use nonoperation instructions to remove branch instructions.

Special on-chip peripherals: The MCF5200M processor, which Motorola designed with its FlexCore methodology, integrates the ColdFire core, debugging module, and misalignment module with a multiply-accumulate (MAC) unit supporting 16- and 32-bit operations. The MCF5202 supports a 32-bit multiplexed bus with dynamic bus sizing that allows access to 8-, 16-, or 32-bit memory and peripherals. It also has a debugging module that provides serial control and visibility of the processor and memory system. Motorola offers the ColdFire2 and ColdFire2M in the FlexCore library for customer design. Both devices integrate the ColdFire core with a debugging module; a misalignment module; and memory controllers that support as much as 32 kbytes each of RAM, ROM, and instruction cache. The ColdFire2M also incorporates the MAC unit.

Development tools: Third-party tools for the ColdFire family include in-circuit emulators from Embedded Support Tools (www.estc.com), Lauterbach (www.lauterbach.com), Microtec International (www.microtec.com), Noral Micrologics (www.noral.com), and Orion (www.yokogawa.com). Cygnus (www.cygnus.com), Diab Data (www.diabdata.com), and Software Development Systems (www.sds.com) offer C compilers. Wind River (www.windriver.com), Integrated Systems Inc (www.isi.com), Embedded System Products (www.esphou.com) offer ColdFire RTOS products. Hewlett-Packard (www.hp.com) offers preprocessor support.

Second sources: There are no second sources for ColdFire.

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