September 24, 1998

EDN's 25th Annual Microprocessor/Microcontroller Directory

hyperstone E1-32X
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The hyperstone E1-32X combines RISC and DSP technology in one core. The E1-32X has a load/store architecture built around a register set that includes 64 general-purpose local and 22 global registers. Local registers are organized into a 64-word, circular register stack to hold function/subroutine stack frames. The stack is organized into frames of as many as 16 words; the E1-32X keeps current frames on chip and automatically pushes the frame to off-chip memory as the register stack fills and moves frames back on chip as the register stack empties. For fast parameter passing, the current stack frame can overlap the previous one with a variable range. Instructions are 16, 32, or 48 bits wide. The variable-length instructions, which the E1-32X automatically prefetches, provide constants and native addresses as large as 32 bits.

The 4-Gbyte address space divides into four blocks; you can configure each block individually for bus width and timing. You can use these blocks for glueless connection of DRAM, extended-data-out DRAM, SRAM, EPROM, or other memory devices, each with its own timing and bus width. A separate I/O-address space also allows each I/O device to have its own timing.

The integrated DSP unit, working in parallel with the ALU and the load/store unit, can perform DSP calculations while the ALU is performing loop counts, address calculations, or load-and-store operations. The ALU executes its instructions during the latency cycles of DSP instructions. The DSP unit shares all the E1-32X's functional blocks, including the register set; however, it provides dedicated result registers and 32- and 64-bit hardware accumulators. The DSP unit supports 16- and 32-bit data types.

Power management: In automatic power-down mode, only the interrupt logic, clock, and DRAM-refresh logic remain active. Sleep mode also disables DRAM refresh. At 3.3V, current consumption in power-down and sleep modes is less than 2.5 mA and 100 µA, respectively.

Special instructions: DSP instructions include multiply, complex and real multiply-accumulate, multiply-subtract, and complex addition/subtraction. Other special instructions include test-leading zeros.

Special on-chip peripherals: Hyperstone's E1-32X contains a DRAM controller that allows you to program page size, refresh rate, timing, and access parameters with an internal-memory register. The controller supports fast-page-mode and extended-data-out DRAMs. The µP also contains a single-cycle-access, 8-kbyte memory, and an I/O- and peripheral-interface controller. You can use this controller to set the width and timing of the µP's address areas. An integrated PLL allows you to multiply the external clock by a factor as large as 4.

Development tools: The vendor offers a development starter kit, a PC-based development board, and the hyICE serial connector for stand-alone operation. The company also provides an ANSI C compiler and DSP library, a source- and task-level debugger, a multitasking real-time kernel, an assembler, a linker, a library manager, and a profiler. Eonic Systems (www.eonic.com) and Etnoteam (www.etnoteam.com) provide RTOS support. Visual Tools (www.etnoteam.it) offers a JPEG embedded-image-compression/decompression library for the hyperstone E1-32X µP. The library supports user-defined subsampling for image quality and compression to the desired size. Hyperstone provides speech compression/decompression algorithms (G.726, G.729, G.723.1, GSM 06.10) and a complete modem. GAO Research (www.gaoresearch.com) offers V.22 modem code.

Second sources: LG Semicon (www.lgsemicon.co.kr) is a licensee.

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