September 24, 1998

EDN's 25th Annual Microprocessor/Microcontroller Directory

Motorola MCore
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MCore uses a four-stage pipeline to execute two-thirds of its 95 basic instructions in one clock. Similar to Hitachi's 32-bit SuperH architecture, MCore uses 16-bit, fixed-length instructions and a register file with 16 general-purpose registers and an alternative register file for context switches. Unlike SuperH, which shadows only eight of its general-purpose registers, MCore shadows all 16. MCore implements only 86% of its operation-code space, allowing some instruction head room for future generations. The 16-bit instruction size forces MCore to use two operand instructions—4 bits per register. Motorola claims that the lack of three operand instructions causes a 2 to 7% code bloat in key applications.

The architecture supports 8-, 16-, and 32-bit data types, although misaligned data accesses force a misaligned data exception. You can mask the misaligned data exception using a control bit in the process-status register. Although you can't access MCore's registers as bytes and words, instructions can sign-extend non-32-bit data types. A barrel shifter shifts as many as 32 bits in one cycle. The architecture also contains a find-first-one unit and result-feed-forward hardware. The feed-forward hardware allows a subsequent operation to use a result while the CPU writes the result back into the register file. The first version of the MCore architecture offers limited support for hardware multiply and divide; it uses a 2-bit per clock, overlapped-scan, modified Booth algorithm with early-out capability to reduce execution time for operations with small multipliers.

MCore contains a 32-channel interrupt controller. The processor can take in an asynchronous interrupt and get to the first instruction of an interrupt-service routine in six clocks. The CPU determines interrupt prioritization through software, and you can use the find-first-one instruction to scan for the highest priority interrupt and use the resulting value as an offset into a jump table. An interrupt-control bit in the program-status register allows an event to interrupt multicycle instructions, such as the load/store multiple-register instructions. For applications that are less real-time-critical, you can set this bit to prevent the interrupts from breaking into instructions.

MCore's hardware-accelerator interface supports a variety of application-specific functions. You can use one of several interface mechanisms. For example, a register-snooping mechanism reflects updates of MCore's registers across the interface without explicit passing of parameters from the core to the hardware accelerator.

Power management: Besides a 16-bit external interface to minimize power consumption, MCore also implements three software-controlled low-power modes and controls functional-unit clocking. The core runs as low as 1V, although the first products operate from 1.8 to 3.3V.

Development tools: To support the development tools for MCore, Motorola has established a validation center to ensure that third-party vendors comply with the Motorola-defined Application Binary Interface (ABI). ABI ensures that MCore tools will work together in a development environment. Although MCore has limited tool support, the tools that are available should handle most development needs. Diab Data (www.diabdata.com) supplies a C/C++ compiler, and Motorola offers a Gnu tool kit. Software Development Systems (SDS, www.sdsi.com) supplies a simulation and debugging tool that offers memory and peripheral simulation. Integrated Systems Inc (www.isi.com) and Microtec (www.microtec.com) have ported their pSOS+ and OS-9000 RTOSs, respectively, to the MCore architecture. Hewlett-Packard (www.hp.com) offers a hardware-based runtime controller that operates through the on-chip emulation circuitry and MCore's JTAG interface. Motorola also offers the MCore V1 evaluation system (EVS) that comprises a µC-memory board, an I/O-personality board, and a test-interface board. These boards provide 512 kbytes of fast static RAM (zero wait states at 20 MHz); 2 Mbytes of flash; 64 bits of general-purpose input or output; and peripherals, including two controller-access-network interfaces, a queued serial module, a queued ADC, and others; and logic-analyzer connectors. The EVS also includes evaluation copies of the SDS debugger and Diab Data compiler.

Second sources: Lucent Technologies (www.lucent.com) has licensed the MCore technology.

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