September 24, 1998

EDN's 25th Annual Microprocessor/Microcontroller Directory

MIPS R3000
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MIPS (www.mips.com) built the MIPS R3000 processors around a set of 32-bit, general-purpose registers in a central register file. To minimize control logic and improve speed, the instruction set has only 73 instructions, and addressing options are few. The chip has a three-address load/store architecture. Similarly, instructions are one 32-bit word to minimize decoding and speed processing. To reduce code size, MIPS and LSI Logic codesigned the MIPS16 application-specific extension. MIPS16 comprises new 16-bit instructions with a corresponding decoding block that the MIPS µP core integrates. Although most applications still need to run 32-bit code (MIPS16 supports a mixture of 32- and 16-bit code), MIPS claims that MIPS16 provides an overall memory savings as large as 40%. LSI Logic, with its TinyRISC TR4101, is the first MIPS licensee to implement the MIPS16 instruction extensions.

MIPS engineers implemented a five-stage pipeline: instruction fetch, read operand and decode instruction, execute, access data memory, and write back results for the R3000. The pipeline lets as many as five instructions execute concurrently—each at a different stage of its instruction cycle. A branch-delay slot minimizes branch effects. The compiler fills the instruction slot, following the branch with a no-operation instruction or an instruction from the current thread that can execute before the branch takes effect. Toshiba's R3900 and Integrated Device Technology's (IDT) RISCore32300, R3000 derivatives, incorporate register "scoreboarding" to enable nonblocking loads and avoid pipeline stalls when there are no data dependencies in subsequent instructions. This feature has a significant benefit in communications applications: It allows programmers to hide main-memory latencies during routing or packet processing. On IDT's 32300, you can also use the nonblocking load for cache prefetch and for performing DMA transfers without performing invalidates and write-backs. IDT implemented this feature as a new hint, called "ignore hint." This feature helps you get around the MIPS instruction-set architecture's lack of "move-multiple" operations. The 32300 also supports a mechanism to minimize pipeline stalls; in the event of a cache miss, the first entering word goes directly to the pipeline.

To improve the multiply and divide performance of the standard R3000, IDT built in a dedicated integer multiply/ divide unit. In the MIPS instruction-set architecture, multiply and divide use special destination registers, permitting only one multiply at a time. IDT enhances this capability with a three-operand multiply, whereby the operand results go directly to a general register. This feature supports DSP capability and performs atomic multiply adds and multiply subtracts. It also implements count-leading ones and zeros operations. The multiply-add throughput is one cycle faster than the data latency, so if you use two distinct operands, the operation becomes load-bound. Whereas the general MIPS mechanism supports reset, cache/parity error, user translation-look-aside-buffer (TLB) miss, and general interrupts, IDT's 32300 lets you define separate interrupts to support software compatibility with your legacy code.

The standard R3000 memory-management unit includes a fully associative, 64-entry TLB that translates virtual addresses to 32-bit physical addresses. (Note: Not all R3000 derivatives contain the TLB.) The µP uses a write-through cache policy. A small on-chip FIFO buffer enables the CPU to perform instruction "streaming"—refilling the cache and executing instructions even while reading additional instructions from memory.

Special instructions: The R3000 implements the MIPS-I instruction set. IDT's 32300 uses the MIPS II instruction-set architecture but includes some MIPS-IV functions. It implements those MIPS-IV instructions, such as prefetch operations and conditional moves, that are independent of operand size. The 32300 also supports both big- and little-endian data types. Several of the MIPS derivatives add a multiply-accumulate (MAC) instruction. LSI is the first MIPS licensee to implement MIPS16 instruction extensions on the TinyRISC TR4101. Toshiba's TX19 also uses the MIPS16 instruction extensions. (See R4xxx, pg 169, for more details.)

Special on-chip peripherals: Philips offers the TwoChipPIC, which combines the UCB1200 that interfaces with the company's PR31700 MIPS µP. The TwoChipPIC provides a microsystem on a chip for handheld devices. Integrated modules include a MAC unit, an LCD controller, an infrared controller, PCMCIA-card support, touchscreen control, and audio in/out. Toshiba's peripherals include a graphics controller, a PCI controller, and support for Microsoft's (www.microsoft.com)Windows CE.

Development tools: A range of third-party development tools is available for the MIPS RISC architecture. Detailed information is available in the MIPS RISC Resource Catalog from MIPS Technologies Inc or at www.mips.com. Philips supplies the hardware-abstraction layer, device drivers, a reference design, and a development board for Windows CE implementation on the TwoChipPIC. Microsoft's Visual C++ tool chain supports TwoChipPIC development.

LSI Logic offers evaluation boards and kits for its line of TinyRISC and MiniRISC µPs and cores. For example, the company's BDMR4101 evaluation board uses an 81-MHz TR4101 CPU core and features 1 Mbyte of SRAM and an 8-Mbyte plug-in DRAM single-inline-memory module, 512 kbytes of flash, a full-duplex serial port, SCN2681 dual UART with dual RS-232C ports, the DP83934 Sonic Ethernet controller with a 10BaseT interface, and the SerialICE debugging monitor and software in EPROM. It supports both PC and Unix host environments. LSI offers a number of tools, including the Mini-SIM and TinySIM architectural simulators for system-on-chip embedded applications, as well as a system-verification environment for silicon-design verification. LSI Logic also provides application-specific evaluation boards, such as the Integra for set-top-box development and the ATMIzer II for communication-product development.

IDT's 33-MHz 79S381 evaluation board allows you to evaluate the 3041, 3052, and 3081 µPs. The board features 2 Mbytes of interleaved DRAM, expandable to 16 Mbytes; 256 kbytes of zero-wait-state SRAM; 512 kbytes of EPROM, expandable to 2 Mbytes; and a 1024-bit serial EEPROM. The company provides the 79S361 evaluation platform for the 79R36100. This board has 1 Mbyte of noninterleaved, zero-wait-state DRAM, expandable to 64 Mbytes. It also contains 2 Mbytes of EPROM and a slot for 1 Mbyte of zero-wait-state SRAM.

IDT offers its kernel-integration tool that includes source- and object-code versions of common routines for CPU design. The company also offers a system-integration monitor that is a ROMable debugging kernel. The monitor includes IDT's micromonitor, which requires only a UART and ROM to perform the initial debugging and integration of new hardware. IDT/C is an ANSI C-compliant Gnu compiler, assembler, linker, and librarian. It includes start-up code, cache, and exception routines.

Toshiba offers evaluation boards for its TX39 products. These boards feature support for serial, SCSI-II, Ethernet, or VMEbus interfaces. Wind River's (www.windriver.com) VxWorks and Tornado RTOS support these boards. Toshiba also offers the TMPR3912 and TMPR3922 reference development systems that support the Microsoft Window CE operating system.

Second sources: MIPS licenses the R3xxx processors to IDT, LSI Logic, NKK, Philips, and Toshiba.

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