September 24, 1998

EDN's 25th Annual Microprocessor/Microcontroller Directory

Fujitsu SPARClite
	View block diagram

Fujitsu based its MB8683x, or SPARClite, family on V8E spec, SPARC International's (www.sparc.com) embedded specification. The family features a 32-bit ALU and uses a load/store architecture with a register stack of 136 32-bit registers. (The 86933H chips have 104.) Eight reserved registers hold global values. The remaining registers arrange into eight overlapping register windows, one for each subroutine. This setup speeds procedure calls and interrupt processing. Multiple contexts can be present concurrently by limiting the number of registers for a task.

Fujitsu engineers extended the SPARC pipeline for the SPARClite family to fetch, decode, execute, memory, and write-back stages. The memory stage minimizes the effects of load/store operations and reduces a load/store to one-cycle execution. The stage is idle for nonload/store operations.

All SPARClite µPs have separate data and instruction caches. The caches are two-way set-associative and have 16- or 32-byte cache lines. You can lock and not swap out critical cache lines on chip. The MB86832 also incorporates a debug-support unit and an emulator bus, which makes instruction streams visible even in on-chip cache. Debugging registers hold data values or addresses for individual and range breakpoints.

The SPARClite processors run with DRAM, synchronous DRAM, SRAM, and ROM/EPROM. The memory interface handles page-mode DRAM for low-cost, high-speed access using a 32-byte burst mode. The memory interface includes a refresh generator for DRAMs, programmable wait states for slower memory, and programmable chip selects for memory banking. Boot-up memory interfaces are programmable; SPARClite CPUs can boot from 8-, 16-, or 32-bit ROM/EPROM.

Power management: SPARClite processors incorporate power-down modes, and a power-management register controls shutdown of the floating-point unit.

Special instructions: The SPARClite implements the SPARC V8 specification, which includes a hardware multiply instruction and a software division using divide by 4. Other special instructions include scan word looking for first changed bit or first one or zero, load/store double word, save/restore caller (uses register windows), tagged add/subtract (generates overflow if most significant bits 0 and 1 are not 0), atomic math and swap, and generate trap from conditions.

Special on-chip peripherals: SPARClite processors come with a 24-bit timer that has an 8-bit prescaler and a 16-bit counter. You can program this counter to operate in periodic-interrupt, time-out-interrupt, or square-wave-generator mode. The µP's debug-and-support unit (DSU) comprises two 4-bit emulator buses for data and status and two control signals that enable and set the breakpoint of an in-circuit emulator for hardware debugging and software development. The SPARClite's DSU has six breakpoint-descriptor registers and supports five hardware-monitoring debugging modes.

Development tools: SPARClite shares many of the development tools that support the SPARC architecture, including compilers and debuggers. Fujitsu supplies $89 evaluation kits and full-featured evaluation boards and monitors. Fujitsu works with Wind River Systems (www.windriver.com), Chorus Systems (www.sun.com), Accelerated Technology (www.atinucleus.com), Microtec (www.microtec.com), JMI (www.jmi.com), Integrated Systems (www.isi.com), and Lynx (www.lynx.com) for RTOS support. These vendors also supply system calls and library routines, many device drivers, and network protocols. Cygnus (www.cygnus.com), Wind River, and Green Hills Software (www.ghs.com) development environments also support SPARClite. Orion Instruments (www.yokogawa.com) in-circuit emulators support SPARC-lite-based system development. US Software (www.ussw.com) and Log Point (www.logpoint.com) offer floating-point libraries for SPARClite.

Second sources: There are no second sources for SPARClite.

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