September 24, 1998

EDN's 25th Annual Microprocessor/Microcontroller Directory

NEC V800
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NEC's V800 Series µCs are available as cores and standard products. All core versions contain the same peripherals as those in the standard devices. The company based the V800, including the V830 and V850, on a proprietary, 32-bit RISC architecture. NEC designed the V830 for embedded multimedia applications with external-memory support; the family provides on-chip instruction and data caches with demultiplexed address and data buses. The V850 is a µC with integrated RAM, ROM, and flash options.

The V800 architecture comprises a five-stage pipeline: fetch, decode, execute, memory access, and write back; 32 general-purpose registers; a 32-bit barrel shifter; and a hardware multiplier. Most instructions execute in one clock and are 2 bytes long, allowing smaller code. The CPU has a pipeline-stall feature that automatically inserts a bubble in the pipeline to avoid data dependencies and hazards. Instruction and data accesses occur on separate buses. Interrupt latency from an external source or peripherals is a minimum of 11 CPU cycles.

A bus-control unit (BCU) generates a prefetch address to prefetch an instruction code from external memory and store it in the 4-double-word prefetch queue. For accesses from internal ROM, instructions go straight to the CPU; that is, not through the prefetch queue. Instruction fetches from internal ROM consume one cycle; data fetches from ROM require three cycles. Therefore, you should shadow look-up tables and fixed data structures to the CPU's internal RAM, in which the V800 can access data in one clock. The BCU also provides a bus-arbitration function, allowing other devices, such as DMA, to share and take control of the V851's external bus. Programmable wait- and idle-state insertion control facilitates interfacing to slow memory. Although most of the microcontrollers provide as much as 16 Mbytes (24 address bits) of linear addressing, the new V850E also provides dynamic bus sizing. The maximum addressing range of the V800 architecture is 4 Gbytes.

The V800 accesses peripherals as memory-mapped I/O that connects to the CPU through a 16-bit bus. ROM and RAM communicate to the CPU using a 32-bit bus. Although the first member of this family, the V851, has 32 kbytes of ROM and 1 kbyte of RAM, the V850 architecture allows internal expansion to 1 Mbyte of ROM and 4 kbytes of RAM. Similarly, the external bus of the V851 addresses as much as 16 Mbytes. (The architecture allows access to as much as 4 Gbytes on future chips.) The V850's memory space divides into 1-Mbyte unit blocks, and you can insert wait states in a bus cycle for every two blocks.

Power management: In halt mode, the clock generator continues to operate, but the CPU clock stops, allowing the on-chip peripherals to function. Idle mode stops the CPU clock and internal-system clock; however, because the clock generator continues to run, normal operation can resume without waiting for oscillator and PLL stabilization. In stop mode, everything stops, but register and memory contents stay intact.

Special instructions: NEC's V800 devices support a software-trap instruction. The CPUs also perform saturate operations in which the devices store maximum values of additions that result in overflow. For example, if the result exceeds the positive-value 7FFFFFFFh, the CPU stores 7FFFFFFFh in the result registers and then sets the saturation flag. The V850E device also provides single-cycle byte-swapping operations for endian translation of data structures. Also, NEC includes single instructions to assist in C procedure calls for pushing and popping multiple registers. The net effect would be a decrease of code in the prologue and epilogue sections in C and a resulting speed increase.

Special on-chip peripherals: An on-chip DRAM controller, synchronous flash controller, and DMA controllers are available in the latest devices.

Development tools: NEC, Green Hills Software (www.ghs.com), and Cygnus Support (www.cygnus.com) offer C-compiler tool chains for the V800. Accelerated Technology (www.atinucleus.com), Green Hills Software, NEC, JMI Software (www.jmi.com), and Wind River Systems (www.windriver.com) provide RTOSs. A host of stand-alone evaluation boards, PC ISA-bus evaluation boards, and in-circuit emulators is available from NEC and third-party vendors. NEC works jointly with Synopsys (www.synopsys.com) and Mentor (www.mentor.com) to provide simulation tools for the V800 Series embedded core/ASIC development. NEC's OpenCAD environment supports these tools and is compatible with the standard device-development tools.

Second sources: There are no second sources for the V800, but Lucent Technologies (www.lucent.com) licenses the V850 as a core within its cell-based ASCI library.

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