September 24, 1998

EDN's 25th Annual Microprocessor/Microcontroller Directory

MIPS R4xxx
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Applications for the R4xxx µPs range from games to laser printers to workstations. Most R4xxx processors implement the MIPS III-architecture instruction set, which provides 64-bit integer registers, 64-bit instructions, and 32- or 64-bit addressing for each privilege level. The first device to implement the MIPS III architecture was the high-end R4000/R4400.

The superpipelined R4400 has an eight-stage pipeline: instruction fetch (first and second halves), register file (access), execute, data cache (first and second halves), tag check, and write back. The drawback of a long pipeline becomes obvious when the processor performs branches or memory references: Branches cause a latency of three internal clocks, and loads incur a two-cycle latency. However, superpipelining increases performance because each stage can run at twice the system clock.

The R4600/R4700 and derivatives represent the low-cost, low-power end of the R4xxx product family. These CPUs include an instruction-fetch, decode, execute, data-cache-read, and cache-write pipeline. They rely on increasing clock speed to raise performance. The pipeline includes a one-processor-clock delay slot for branch-type instructions. The R4700 includes a separate floating-point unit (FPU) and performs integer multiply and divide in the FPU. (The R4700 has no integer-multiply and -divide unit.) The R4700 does virtual-to-physical-address translation in parallel with its cache accesses. The caches are virtually indexed to speed access but physically tagged for addressing. The R4700 has a 96-entry, fully associative translation-look-aside buffer (TLB). The R4700 checks the cache entry's physical tag against the TLB's physical address. A four-entry write buffer eliminates write stalls.

The R4300i, another R4xxx implementation, reduces its silicon overhead by overlapping the FPU and executing floating-point instructions in the integer ALU; this tactic simplifies the pipeline and eliminates the need for a separate floating-point datapath. To accommodate floating-point operations, the R4300i's integer unit contains 32 64-bit floating-point registers.

Power management: The R4300i's power-management features include a mode that reduces the clock rate to one-fourth of normal and a power-down mode that writes the CPU state to battery-backed RAM before turning off. The CPU has an instruction micro-TLB that caches the last two TLB entries and thus minimizes power dissipation. (The main TLB need not turn on.) Other circuit-design techniques also minimize power dissipation.

Special instructions: MIPS R4xxx processors implement the MIPS III instruction set. To save code space, MIPS16 is an architectural extension that implements new 16-bit instructions. MIPS III's new instructions include double-word loads, stores, shifts, and addition/subtraction. The R4xxx's on-chip FPU performs 32-bit, single-precision and 64-bit, double-precision, floating-point operations. It performs integer multiply and divide stepwise in bit pairs and single bits, respectively. The chip handles 32- and 64-bit multiplies and divides. It seamlessly uses 32-bit arithmetic results in 64-bit computations; you need not track operands and specify conversion. Integrated Device Technology's (IDT's) R4640/50 has an atomic multiply-add operation to perform multiply-accumulate operations. This instruction, which DSP algorithms use, multiplies two numbers and adds the product to the contents of the high and low registers.

Special off-chip peripherals: NKK supports its 4xxx products with the Big and Little Dipper chip sets. The Big Dipper features CPU-interface control, an L2-cache controller, a PCI-bus bridge, an external PCI-arbiter interface, and a memory controller. The Little Dipper, targeting embedded applications, interfaces to the CPU and features ROM, DRAM, and DMA controllers; a timer/counter; an interrupt controller; a PCI arbiter; and a PCI interface.

NEC provides companion chips for the VR4XXX line. The VRC4171 adds color-LCD-graphics-controller capability and four programmable general-purpose I/O pins. The VRC4373 adds a PCI interface, a DMA controller, boot ROM support, and DRAM control.

Galileo Technology (www.galileot.com) provides system core-logic and PCI-interface devices for a variety of MIPS devices. For example, the company's GT-64014 system controller for the R4640 CPU supports page-mode and extended-data-out DRAM, five independent chip selects, a DMA controller with four channels and separate FIFO buffers, three 24-bit timers and one 32-bit timer, and an interrupt controller for on-chip interrupt sources.

Development tools: Cygnus (www.cygnus.com) and Tasking (www.tasking.com) provide C compilers, linkers, debuggers, and assemblers for the R4000. You can develop on a Sun, Solaris, or Windows NT/95 platform.

IDT's 79S465 evaluation platform supports the 79RV4700 µP and operates at 50 MHz for the system and memory interfaces. The board features 4 Mbytes of noninterleaved DRAM, expandable to 64 Mbytes; 2 Mbytes of noninterleaved and cacheable flash; and 4 Mbytes of interleaved, zero-wait-state SRAM. The addition of the 79R440 daughtercard lets you use the 79S465 board to evaluate IDT's 79RV4650 and 79RV4640 µPs. IDT also offers software tools for its R4xxx processors. (See the MIPS R3xxx in the 32-bit section of this directory for more information.)

Second sources: MIPS Technologies (www.mips.com) designed and licenses the R4xxx processors to IDT, NEC, NKK, and Toshiba. QED designed the R4600, R4700, R4640, and R4650 MIPS III processors and licenses them to IDT, Toshiba, and NKK.

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