September 24, 1998

EDN's 25th Annual Microprocessor/Microcontroller Directory

MIPS R5xxx
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The MIPS R5xxx, with applications ranging from routers to arcade games to digital set-top boxes, represents a variety of processors that implement the MIPS IV instruction set. The superscalar R5000, which is the first implementation, uses an instruction-fetch, decode, execute, data-cache-read, and write-back pipeline similar to that of the R4000 processor. In addition, the R5000 provides a dual-issue mechanism to allow the device to issue a floating-point instruction simultaneously with any other instruction type.

The R5000 contains 32-kbyte instruction and 32-kbyte data caches. A dual, 48-entry, virtually indexed translation-look-aside buffer (TLB) also increases performance by allowing back-to-back TLB accesses. The TLB implementation is compatible with R4xxx implementations to ensure compatibility with system and user software. The R5000 includes a fast multiplier for floating point with a fused multiply-add, a major improvement over MIPS III CPUs. The CPU also supports an interface to a synchronous L2 cache.

One benefit of the MIPS architecture is that it lets MIPS licensees redesign the basic instruction-set-architecture core to deliver the desired price and performance. For example, NEC based its VR5400 family, which Sandcraft (www.sandcraft.com) designed, on the MIPS IV instruction set and the cache and memory-management unit of the VR5000. The VR5400 is a symmetrical, dual-issue superscalar architecture. Sandcraft modeled each pipeline after the MIPS R4300 integrated integer/floating-point pipeline architecture. The device includes a local bypass that allows information to bypass the write-back stage, feeding data directly back into the pipeline and preventing pipeline locking. The VR5400 also supports global bypass that would allow the two pipelines to exchange results to minimize the effects of data dependencies.

Unlike the R5000, which has separate integer and floating-point pipelines, the VR5400's pipelines can handle either integer or floating-point instructions. This approach lets the core execute any combination of integer/integer, integer/ floating-point, or floating-point/floating-point instructions. To enable each pipeline to handle both integer and floating-point operations, NEC split up the floating-point operations: The mantissa goes through the integer portion of the pipe, and the exponent goes through a separate 12-bit ALU.

Within the two pipelines, the VR5400 has six independent execution units: two unified integer/floating-point units, one nonblocking load/store unit, a 32X32-bit integer/floating-point multiply unit with a 64-bit accumulator, one vector unit that supports an 8X8-byte single-instruction multiple-data (SIMD), and one branch unit. Each integer/floating-point unit contains a 64-bit barrel shifter that can perform single-cycle left or right rotation of 32 or 64 bits.

The multiply unit can perform continuous 32X32-bit single-cycle multiplies and multiply-accumulates (MACs) without stalling the pipeline; however, a 64X64-bit multiply may stall the pipeline. The vector unit uses 64-bit registers that are shared floating-point registers, so the device cannot perform floating-point operations during a vector operation. You have to flush the pipeline when switching between floating-point and vector operations.

QED's RM7000 product family, which is pin-compatible with the company's RM5270, is another example of a licensee's redesigning the MIPS IV instruction-set core to achieve the desired price and performance. The RM7000 is a symmetrical, dual-issue, superscalar architecture with six execution units borrowed from QED's RM52XX family. These units include two integer units, one floating-point unit, one branch unit, one load/store unit, and one integer MAC unit. The family also has hardware support for floating-point multiply and divide instructions.

The RM7000 includes 256 kbytes of unified L2 cache. Both the primary and L2 caches are nonblocking, four-way set-associative with per-line cache locking. QED also added user-mode cache operations to further improve cache usage and to allow complete bypassing of the secondary cache. Additional pins allow RM7000 devices to support as much as 8 Mbytes of tertiary cache. The RM7000 implements a new interrupt scheme that uses prioritization and vectorization to provide a maximum of 166 nsec of interrupt latency if the interrupt routine is in the primary cache. New watch registers allow software designers to tune their code by counting 24 independent events, such as cache hits, cache misses, and branches.

Special instructions: Devices in this family are code-compatible with MIPS I, II, III, and IV. MIPS IV supports four MAC/multiply-subtract floating-point instructions, useful in graphics and signal processing. It also supports conditional moves to reduce branch frequency; index-address modes (register plus register); and new addressing modes for floating-point operations that compilers require for higher performance floating-point throughput.

NEC added register-based multiply instructions to the VR5400; this feature allows the CPU to write the multiply result to a register file instead of to special internal registers (as on the standard R5000). QED supplies six direct derivatives of the R5000 in its RM52xx and RM52x1 families. Each of these processors uses the same CPU model with instruction-set enhancements for integer multiply-add and three-operand multiply.

Special off-chip peripherals: Galileo Technology (www.galileot.com) provides multiple chips that support the R5000, RM52xx, and RM52x1 chips for programmable interrupt controllers, memory, and L2 caches. The GT-64120 provides a system controller that features a CPU interface, two 32-bit PCI interfaces, a memory interface, four DMA channels, and timers. The GT-64010 supports a CPU interface, a PCI interface, a memory interface, four DMA channels, and timers. The Galileo GT-64012 provides L2-cache-interface support with the GT-64010.

NEC provides the VRC5074 system controller, which features a CPU interface, an L2-cache controller, a PCI-bus interface, a memory interface, a 32-bit local-bus interface, DMA, UART, and timers. NKK's Big and Little Dipper chip sets support the R5000. The Big Dipper features CPU-interface control, an L2-cache controller, a PCI-bus bridge, an external PCI-arbiter interface, and a memory controller. The Little Dipper, targeting embedded applications, interfaces to the CPU and features ROM, DRAM, and DMA controllers; a timer/counter; an interrupt controller; and a PCI arbiter and PCI interface. Galileo Technology also provides R5000-specific support chips for PIC, memory, and L2 caches. NEC is reportedly planning to provide a similar support chip. V³ Semiconductor (www.vcubed.com) offers support for the RM5230 and RM5231 32-bit memory versions with the USC32 chip.

Development tools: A range of third-party development tools is available for the MIPS RISC architecture. Accelerated Technology (www.atinucleus.com), Green Hills Software (www.ghs.com), Integrated Systems (www.isi.com), Microsoft (www.microsoft.com), QNX (www.qnx.com), and Wind River (www.windriver.com) provide embedded operating-system support. Other OSs are available through the OpenBSD (www.openbsd.org) and Linux (www.linux.org) organizations. Algorithmics (www.algor.co.uk), Cygnus (www.cygnus.com), Embedded Performance Inc (www.episupport.com), Green Hills Software, Metrowerks (www.metrowerks.com), Microsoft, Tasking (www.tasking.com), and Wind River offer development-tool chains and compilers. Corelis (www.corelis.com) and Hewlett-Packard (www.hp.com) offer debuggers and in-circuit emulators. (You can get further information on development tools for the Rxxxx and other MIPS µPs in the MIPS RISC resource catalog at www.mips.com; this catalog does not contain up-to-date information, so the reader should also check the Web sites of the individual semiconductor partners.)

Third-party vendors Algorithmics, Galileo Technology, and Cogent Computer Systems (www.cogcomp.com) provide evaluation boards for the R5000. Mentor Graphics (www.mentor.com) offers bus-functional models, iMODL (www.imodl.com) and Synopsys (www.synopsys.com) offer hardware models, and Summit Design (www.simtech.com) offers a coverification environment and software-development-tool suite.

Second sources: QED designed the R5000 and licensed it to MIPS Technologies (www.mips.com), which, in turn, licensed it to Integrated Device Technology, NEC, and NKK.

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