September 24, 1998

EDN's 25th Annual Microprocessor/Microcontroller Directory

Sun UltraSPARC
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UltraSPARC-I, -II, and -III are silicon implementations of SPARC V9, a version of the scalable-processor architecture. SPARC V9 maintains upward binary compatibility with SPARC V8 and extends the architecture with support for 64-bit virtual addresses and integer data as large as 64 bits; 32 double-precision, floating-point registers (up from 16); and speculative loads, which don't take a fault if accessing an out-of-range variable. V9 also defines a hardware mechanism that uses compiler technologies that streamline the prefetching of data and instructions.

The UltraSPARC-I and -II superscalar processors have nine-stage pipelines in which the first two stages comprise the instruction fetch and decode. Sun adds three stages to the integer pipe to make it symmetrical with the floating-point pipe. This architecture simplifies pipeline synchronization and exception handling; it also eliminates the need for a floating-point queue. The CPU's pipeline encompasses two integer ALUs, five graphical floating-point units, and a load/store unit. Sun also includes a 2-bit dynamic branch-prediction mechanism, which is part of the UltraSPARC's prefetch unit. As the 16-kbyte instruction cache fills, the CPU uses 2 extra bits per instruction to tag information related to the branch prediction for that instruction.

UltraSPARC-III, Sun's third generation of SPARC, implements a 14-stage nonstalling pipeline. The first three stages include instruction fetch and decode, the next three stages include branch prediction and instruction queuing, and the next stage is for register-file reads. The execution stages comprise integer and floating-point/graphics pipelines, each with five stages. Two final stages handle traps and complete the pipeline. The UltraSPARC-III can issue as many as eight instructions—four integer, two floating point, and two graphics—per cycle. It can also support multiprocessor scaling to more than 1000 processors and has a 16,384-entry, history-based, branch-prediction mechanism, which uses a 20-entry instruction queue and a four-entry miss queue.

UltraSPARC-I uses data buffers to isolate the L2 cache from the system bus. These buffers enable overlapping of system transactions and perform error detection and correction. The processor contains an on-chip, L2-cache controller, and the system bus can run at one-half to one-third the processor frequency. Sun claims that instructions and data can pass between the L2 cache and the CPU at 2.6 Gbytes/sec.

The UltraSPARC-IIi is the first member of Sun's new UltraSPARC i-Series family of integrated processors. Each functional area on the UltraSPARC-IIi maintains decentralized control, allowing activities to overlap. A decoupled prefetch and dispatch unit provides sustained performance for as many as four instructions per cycle. UltraSPARC-IIi can handle multiple outstanding memory requests—three loads and two stores versus one load or store for UltraSPARC-I. Sun offers the UltraSPARC-IIi as an individual component, on an integrated cache-based module, and on industry-standard boards.

Special instructions: SPARC V9 adds several instructions to the V8 specification. The new instructions are conditional move, 64-bit integer multiply/divide, compare and swap, prefetch, and branch-on-register-value instructions. UltraSPARC adds the visual-instruction set of graphics instructions (not in SPARC V9). These instructions provide the most common operations to support Java, networking, and graphics acceleration.

Special on- and off-chip peripherals: The UltraSPARC-IIi features three integrated interfaces: a memory controller for industry-standard DRAM access; an Ultra Port Architecture (UPA) controller supporting access as fast as 6.4 Gbps; and a 32-bit, 66-MHz, 3.3V PCI interface.

Sun's Advanced PCI Bridge (APB) chip supports the UltraSPARC-IIi. This I/O ASIC has a 32-bit, 66-MHz primary bus and two independent 5V, 32-bit, 33-MHz secondary buses with full prefetch support. You can attach as many as four APB chips to the UltraSPARC-IIi, enabling support for as many as 32 industry-standard PCI devices. The UltraSPARC Data Buffer isolates the processor and its external cache from the main-system data bus, allowing the interface to operate at processor speed. The SYSIO system-I/O chip bridges the UPA and I/O bus. Sun also offers two bridge chips for the Sbus (U2S chip) or the PCI (U2P chip). A crossbar switch, the buffered multiplexer, helps control traffic on the system's data buses.

Development tools: UltraSPARC support is available from Sun's popular Solaris and Java OSs as well as from an array of third-party RTOSs and development tools for embedded applications. Sun offers an architectural simulator that performs cycle- and instruction-accurate simulation.

Second sources: There are no second sources for the UltraSPARC families.

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