September 24, 1998

EDN's 25th Annual Microprocessor/Microcontroller Directory

Intel 8051
	View block diagram

The 8051 is an accumulator-based design with 255 instructions. A basic instruction cycle takes 12 clocks; however, Dallas Semiconductor redesigned the instruction-execution circuitry to reduce the instruction cycle to four clocks for most instructions. The 8051 has a minimum 39-clock latency from the assertion of an interrupt to the beginning of the first instruction of an interrupt-service routine.

The CPU has four banks of eight 8-bit registers in on-chip RAM for context switching. These registers reside within the 8051's lower 128 bytes of RAM along with a bit-operation area and scratchpad RAM. You can address these lower bytes directly or indirectly using an 8-bit value. The upper 128 bytes of on-chip data RAM encompass two overlapping address spaces. One space is for directly addressed special-function registers (SFRs); the other space is for indirectly addressed RAM or stack. The SFRs define peripheral operations and configurations. The 8051 also has 16 bit-addressable bytes of on-chip RAM for flags or variables.

Without external support circuitry, the theoretical maximum address range of all 8051 processors is 64 kbytes of program memory and 64 kbytes of data memory. However, software tools with an external latch allow you to increase this address space to any number of 64-kbyte pages. The software seamlessly handles all page transitions.

Register indirection uses an 8-bit register for an on-chip RAM address; an off-chip address needs an 8- or 16-bit data-pointer register (DPTR). The 8051 has only one DPTR (Atmel, Dallas, and Philips µCs have two DPTRs; Siemens µCs have eight DPTRs). You cannot index the DPTR; however, you can increment the 16-bit DPTR. You can index program-memory accesses using move-code instructions for look-up tables or constants. The CPU has bidirectional and individually addressable I/O lines.

Power management: Idle mode discontinues CPU processing but leaves the clock, timer, serial-peripheral-interface, and serial-communications-interface systems enabled. Power-down stops the clock and all internal processing. Both modes maintain RAM and, for some of the 80C51 derivatives, enable interrupts to wake the CPU. You can program and selectively turn off most peripherals. Dallas and Siemens devices also provide programmable-clock divisors. Dallas' devices can automatically return to full-power operation as a result of an external interrupt or incoming serial character.

Special instructions: The 8051 performs extensive bit manipulation via instructions, such as set, clear, complement, and jump on bit set or jump on bit clear, only for a 16-byte area of RAM and some SFRs. It can also AND or OR bits with a carry bit. Dallas versions have variable-length move-external-data instructions. Math functions include add, subtract, increment, decrement, multiply, divide, complement, rotate, and swap nibbles. Some of the Siemens devices have a hardware multiplier/divider for 16-bit multiply and 32-bit divide.

Development tools: The 8051 has extensive tool support. Emulators are available from such companies as Nohau Corp (www.nohau.com), Hitex GmbH (www.hitex.com), and MetaLink (www.metalink.de). Tasking (www.tasking.com) and Keil Software (www.keil.com) offer compiler and software-development support. Data I/O (www.dataio.com) offers programming support. In addition, most 8051 vendors provide evaluation kits. Several RTOS vendors, including CMX Co (www.cmx.com), Franklin Software Inc (www.franklinsoftware.com), and Keil, also support the 8051.

Second sources: Second sources for the 8051 are Atmel, Dallas, Intel, Oki, Philips, Siemens, and Temic.

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