September 24, 1998

EDN's 25th Annual Microprocessor/Microcontroller Directory

Intel MCS 151/251
	View block diagram

The MCS 151 and 251 cores are binary-code-compatible with the 8051. (The 251 has additional instructions.) The 151 maintains the 80C51 accumulator-based core compatibility, and the 251 is a register-based architecture. Both cores have a three-stage pipeline that allows the CPU to run at a minimum of two clocks per instruction cycle (versus 12 clocks for the 8051 or four clocks for the Dallas Semiconductor version). The 251 CPU comprises an 8-bit ALU, an instruction sequencer, a 24-bit program counter, a 40-byte register file, and four banks of eight registers. You can address its register file as bytes, words, or double words, and all registers are available as register pointers (versus the single data pointer of the 8051).

The MCS 151 and 251 have an internal, 16-bit-wide instruction bus that supports a 16-bit fetch per cycle from the internal code memory through the CPU's bus-interface unit. The data bus is 8 bits wide. To handle large applications, the MCS 251 architecture can perform 24-bit linear addressing for a 16-Mbyte memory space. (Implementations may vary, however.) The 251 and 151 also have programmable wait states and page mode, and you can select extended address-latch-enable capability with a user-programmable configuration.

Power management: Idle mode discontinues CPU processing but leaves the clock, timer, serial-peripheral-interface, and serial-communications-interface systems enabled. Power-down stops the clock and all internal processing. Both modes maintain RAM and enable an interrupt to wake the CPU. You can program and selectively turn off most peripherals.

Special instructions: The MCS 251 has new instructions as well as the instructions the 8051 supports. New instructions include 16-bit arithmetic and logic instructions, conditional jumps, and a jump to the location, depending on the result from the previous instruction.

Special on-chip peripherals: The programmable counter array comprises a 16-bit timer and five compare and capture modules. You can use each compare and capture module in rising- and falling-edge-capture, software-timer, high-speed-output, or PWM mode. You can also use the fifth module as a watchdog timer.

Development tools: Intel and third-party vendors provide a range of development tools and services to support the 151/251 architecture. Tools include emulators, evaluation kits, programmers, development software, logic analyzers, and RTOSs. Examples of emulators include the Emul251-PC from Nohau (www.nohau.com), AX251 from Hitex GmbH (www.hitex.com), and ICEmaster from MetaLink (www.metalink.de). Data I/O (www.dataio.com) provides programming support. Software tools include Compass/251 from Production Languages (www.plcorp.com), the DK251 developers kit from Keil Software (www.keil.com), and tools from Tasking (www.tasking.com). (For more information about tools, go to http://developer.intel.com/sites/developer/.)

Second sources: Temic Semiconductors offers a 251 with an ADC.

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