September 24, 1998

EDN's 25th Annual Microprocessor/Microcontroller Directory

STMicroelectronics ST9
	View block diagram

The nucleus of the ST9 comprises a core that includes the CPU, the register file, interrupt and DMA controllers, and the memory-management unit (MMU). The MMU lets you address as much as 4 Mbytes of program and data memory mapped into one linear space. The ST9 has a 22-bit memory bus, an 8-bit register-addressing bus, and a 6-bit interrupt/DMA bus. The interrupt/DMA bus connects the interrupt and DMA controllers in the on-chip peripherals to the core.

The CPU, with 94 instruction types, manages the 256-byte register file as 14 sets of 16 8-bit, general-purpose registers. (The 15th set is the system page, and the 16th set is addressed as peripheral registers.) Switching from one set of registers to another allows fast context switching because the CPU need not save or restore registers. The CPU also contains an 8-bit program-status register. You can use the general-purpose registers as accumulators, index registers, or address pointers. Adjacent register pairs constitute 16-bit registers for addressing or 16-bit processing. Although the ST9 has an 8-bit ALU, the chip handles 16-bit operations, including arithmetic, loads/stores, and memory-to-register and memory-to-memory exchanges. Many operation codes specify byte or word operations; the hardware automatically handles 16-bit operations and accesses. A 2-byte operation-code+displacement instruction usually requires two memory fetches; a 16-bit instruction takes only one fetch.

For interrupts or subroutine calls, the CPU uses a system stack with the stack pointer. A separate user stack has its own stack pointer. The separate stacks without size limitations can be in the on-chip RAM, register file, or off-chip memory.

Power management: The ST9 implements slow, wait-for-interrupt, and halt modes. In slow mode, a CPU prescaler and clock-control unit reduce the clock frequency to the CPU and peripherals. In halt mode, the CPU and its peripherals stop operation, and the I/O ports enter high-impedance mode if the watchdog timer is disabled. The system must assert a reset for the CPU to exit halt mode.

Special instructions: The ST9 instruction set includes instructions for bit handling, 8-bit byte data, and 16-bit word data, as well as BCD and Boolean formats. Other instructions facilitate large program and data handling through the MMU, as well as improve the code density of C function calls. The ST9's bit-manipulation instructions are set, clear, complement, test and set, and load, and the ST9 can perform AND, OR, and XOR logic instructions on any register. Math functions include add, subtract, increment, decrement, decimal adjust, multiply, and divide. The ST9 has 14 addressing modes, including indirect-addressing capabilities.

Special on-chip peripherals: The 16-bit multifunction timers of the ST90158 and ST90135 each have an 8-bit prescaler and 13 operating modes. This functionality allows you to use complex-waveform generation and measurements, PWM functions, and other system-timing functions. Two DMA channels support each timer. In addition, these devices contain an eight-channel ADC with S/H and 8-bit resolution. Two of the input channels feature automatic voltage monitoring. The devices also contain a full-duplex serial communications interface with an integral generator, programmable asynchronous and synchronous capability, an associated address/wake-up option, plus two DMA channels. A programmable PLL clock generator lets you use 3- to 5-MHz crystals to obtain a range of internal frequencies as high as 16 MHz.

Development tools: Development-tool support for the ST9 family includes emulators, programmers, assembler/linkers, debuggers, archivers, and a C-compiler chain with source-level debugging capability from Cygnus (www.cygnus.com).

Second sources: There are no second sources for the ST9.

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