September 24, 1998

EDN's 25th Annual Microprocessor/Microcontroller Directory

Toshiba TLCS-90

Toshiba's TLCS-90 incorporates the basic Z80 instruction set in an 8-bit µC with various peripherals. Unlike the Z80, which is a µP, the TLCS-90 can execute code from on-chip ROM and RAM. The µCs feature a Z80-like dual set of eight 8-bit general-purpose registers. You can pair the registers for 16-bit loads, stores, and arithmetic operations. The dual set of registers allows the programs to perform fast context switching and register storage. Two 16-bit index registers, a stack pointer, and a program counter supplement the general-purpose registers. These index registers, as well as 16-bit loads, exchanges, and arithmetic operations, make 16-bit addressing simple. Two 8-bit bank registers extend addressing from 16 to 24 bits, and a memory-management unit extends addressing to 8 Mbytes of data.

The TLCS-90's core uses a two-stage, pseudopipeline architecture to speed operations. In the first stage, the CPU fetches and decodes instructions; in the second stage, the decoded instructions are executed. Instructions have 1 or 2 operation-code bytes. Immediate and address data can take as many as 3 bytes; the maximum instruction length is 5 bytes (2 operation-code and 3 data bytes). The first operation-code byte specifies the position of the second operation-code byte in the instruction stream.

Power management: Idle mode shuts down the CPU, leaving all integrated peripherals active. Power-down (stop) disables the oscillator. A reset or interrupt request can terminate idle mode; only hardware reset (nonmaskable interrupt and Interrupt 0) can terminate power-down.

Special instructions: Bit-manipulation instructions include bit set, clear, test, and various logical operations. Math instructions include multiply-accumulate, add, subtract, decimal adjust, signed 8X8-bit multiply, and signed 16X8-bit divide. The TLCS-90 can also perform block moves and pattern searches in memory.

Development tools: Toshiba provides a C compiler, an assembler, a source-level debugger, a DOS-based controller, and a real-time emulator for each derivative. The controller is common for all derivatives.

Second sources: There are no second sources for the TLCS-90.

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