September 24, 1998

EDN's 25th Annual Microprocessor/Microcontroller Directory

Zilog Z8/Samsung SAM8X
	View block diagram

The register-file-based Z8's core has 50 basic instructions and as many as 256 8-bit registers in RAM. On-chip peripherals are memory-mapped, and you access them through the register file. The RAM also holds the I/O-control registers; 16-bit, two-register stack pointer; and register pointer. The CPU contains a 16-bit program counter and an 8-bit program-status register. In addition to the register file, the Z8 architecture has 64-kbyte code and 64-kbyte data-address spaces. The Z8 allows the use of external memory for both code and data spaces. References to external memory are loads or stores only; data manipulation is confined to operations between on-chip registers. For interrupt-driven applications, the stack may reside off-chip.

Starting this year, Zilog is offering µCs based on a new beefed-up core that the company calls the Z8Plus. Although this core is software-compatible with the traditional Z8, Zilog expects the Z8Plus to outrun the Z8 by as much as 50%. This performance improvement primarily results from a reduced system clock and a fixed instruction-cycle time. All instructions on the Z8Plus execute in five system clocks; the minimum instruction-cycle time for the Z8 is six system clocks, and some instructions require as many as 20 clocks. The fixed-length instruction time not only yields higher perform-ance, but also helps you write more deterministic software.

Zilog also added code-rollover protection to the Z8Plus. An advantage of rollover protection is its instant response to program error; compare this response to the several milliseconds that a watchdog timer may take to time out. On the Z8, address 00h is the first interrupt vector, and it has no instruction associated with it. With the Z8Plus, you can specify a short jump and an address at location 00h.

Some Z8-based chips have the Z8 core plus a DSP engine with a 24-bit ALU; other chips implement IR remote-control functions by incorporating IR signal-generation and -demodulation timers.

Although Samsung based the SAM8 core on Zilog's Z8 architecture, some architectural differences exist. For example, the SAM8X core uses a two-stage, pseudopipeline architecture to expedite instruction processing. In the first stage, the CPU fetches and decodes instructions. The second stage executes the decoded instructions. The maximum instruction length is 5 bytes.

Power management: Halt mode turns off the internal CPU clock while the timers and interrupts remain active. Stop mode turns off the internal clock and reduces standby current. Another advantage of the Z8Plus is its lower power consumption because of fewer clocks per instruction and other design improvements. Although the devices differ in peripherals and memory, Zilog is specifying the first Z8Plus part at 6 mA (5.5V and 10 MHz). Compare this spec with 20 mA for the similarly featured Z86E04 running at 5.5V and 12 MHz.

Special instructions: Bit-manipulation instructions in the Z8 include AND, OR, and XOR logical instructions and some bit-test instructions. Arithmetic instructions include add, subtract, increment, and decrement. Some Z8 devices support 16X16-bit multiply and 32X16-bit divide. The versions with integrated DSPs perform multiply-accumulate operations. Z8 chips include complex instructions that help to minimize coding of multiple operations, such as fetching and operating on data and incrementing address pointers.

Special peripherals: Z8 chips contain power-on-reset circuitry to eliminate the need for an external reset circuit. They also support brownout voltage detection that holds the Z8 in a reset condition while V_CC is below the V_BO spec value. Zilog guarantees that, when the V_BO point is less than the V_CC minimum, the product operates correctly down to the V_BO point. Every Z8 contains voltage comparators that serve as low-cost ADCs. Zilog provides a reference design for rapid battery charging. (For example, the Z8 charges NiCd batteries in 20 minutes.) Every Z8 comprises an 8-bit timer with a 6-bit prescaler, usually viewed as the equivalent of a 14-bit timer. Each timer has an independent interrupt and one timer-output signal.

The Z86C83 and 84 each have an eight-channel, 8-bit ADC that can offset the A_GND level by V_CC/2, giving 10-mV resolution across this range. This feature is important in charging some battery chemistries that require at least 15-mV resolution.

Samsung's KS86C6XXX devices support high- or low-speed Universal Serial Bus functions. The KS88CX4XX µCs, geared toward remote-control applications, have power-on-reset circuitry, eliminating the need for an external reset circuit. They also support brownout voltage detection to hold the µC in a backup condition while V_CC is below the low-voltage spec value. The KS88C9XXX µCs are for Smart Cards, offering such features as software kernel control, secure ROM coding, and unique serial numbers for each chip.

Development tools: Zilog supplies a low-cost in-circuit emulator (ICE) with Windows-based software for the Z8. Samsung's SMDSIIP ICE features real-time trace mode, real-time timer mode, and RAM-break functions for debugging. The SMDSIIP can program the full line of Samsung's one-time-programmable offerings. You can use the base unit of the SMDSIIP as a low-cost, start-up development system. IAR Systems (www.iar.com) provides third-party C-compiler support for the SAM8 series.

Second sources: There are no second sources for the Z8 or the SAM8X.

Back to Microprocessor/Microcontroller Directory Main Page

| EDN Access | Feedback | Table of Contents |

Copyright © 1998 EDN Magazine, EDN Access. EDN is a registered trademark of Reed Properties Inc, used under license. EDN is published by Cahners Business Information, a unit of Reed Elsevier Inc.