October 8, 1998

Optical encoder controls range switch

W Dijkstra, Waalre, The Netherlands

Instead of using a counter-controlled, pushbutton-activated range switch, you can use an optical encoder. Inexpensive encoders are available, and they occupy minimal space on the front panel of an instrument. Moreover, an encoder gives you the opportunity to select the optimum operating speed. However, at positions near the transition points in counter position, mechanical shocks can provoke false switching. The circuit in Figure 1 overcomes the false-switching problem.

Output S0 of the optical encoder controls the up/down inputs of counters IC₁ and IC₂. Output S90 connects to the clock input of the HEF4516 binary counter (IC₁). When this counter reaches 0 or 15, the output CO goes low and clocks (via an inverter) the HEF4510 decimal counter (IC₂). Simultaneously, the binary counter assumes a value of eight. Thus, it requires eight pulses of the optical encoder to alter the position of the decimal counter. You must stop turning the optical encoder within eight pulses, which in practice is eminently possible. When you want more security, you can feed the outputs Q3 and Q4 of the decimal counter to an exclusive OR gate. When the output of the XOR gate is high, changing the state of the decimal counter requires a minimum of four pulses from the optical encoder.

The circuit provides control with bidirectional hysteresis. To stop the decimal counter at zero when counting down, the counter resets when output Q9 of the 1-of-10 decoder HEF4028 (IC₃) goes high. To limit the number of decoder positions, you can load the decimal counter one position lower than the maximum output position you want to reach with the output decoder. The configuration in Figure 1 loads the decimal counter with the value five when Q6 (the seventh position) of IC₃ goes high. (DI #2255).

µC controls digital potentiometer

Lukasz Sliwczynski, University Of Mining And Metallurgy, Krakow, Poland

Many digitally controlled potentiometers (for example, the LM1971/2/3 from National Semiconductor, www.national.com) incorporate a three-wire serial digital interface, using data, clock, and enable lines. In Figure 1, the potentiometer's nomenclature for these lines is Data-In, Clk, and Load/Shift, respectively. The assembler program in Listing 1 provides an interface to an SAB80535 µC. The main idea of the method is to use the capture/compare capability of Timer 2 in the µC to provide the timing relationship between the Data-In and Clk signals. The principal control of the interface comes from subroutine S16BIT in Listing 1.

To program the potentiometer, the µC must send 2 bytes to it—the "channel address," followed by the attenuation value with its most significant bit first. Sending a byte starts by loading the number of bits to send into the µC's BCOUNT register and initiating the P1 lines (setting P1.0 through P1.3 to a low state). Next, Timer 2 starts with overload enabled. The routine sets two digital compare/capture units (CC1 and CC3 in the µC) to the "compare" mode by writing 88H into the CCEN register. The contents of the register decrease after each interrupt. In this way, eight consecutive interrupts occur, each to send 1 bit of data. The interrupt subroutine at address 006BH manages the transmission of the data bits via P1.2.

The CC1 unit generates the Clk signal on pin P1.1 when the contents of the Timer 2 count register (composed of TH2 and TL2 8-bit registers) equal the values set in registers CCL1 and CCH1. This value depends on the length of the interrupt subroutine. After transmission of the last bit, the routine stops Timer 2 by setting the value 0ECH in register T2CON. During data transmission, the main program spends its time waiting in the loop, as long as the bit FLAGS.0 is at logic 1. This bit clears in the last pass of the subroutine and sets just before Timer 2 starts. Transmission of the second byte of data occurs in exactly the same way after the routine reprograms the related registers. The Channel and Volume registers hold the 2 bytes to send.

Figure 2 and Figure 3 show the timing relationships of the interface. In Figure 2, the 2 bytes Channel and Volume are 05AH and 081H, respectively. Data is valid on the rising edge of the Clk signal. Figure 3 shows the time dependence in the interrupt-routine calls and the Clk rising edges. In this design, it takes approximately 740 µsec to program 2 bytes into the potentiometer with an 8-MHz clock frequency (a 1.5-µsec machine-cycle time). (DI #2256).

Timer inputs double as interrupt-request lines

Sk Shenoy, Naval Physical And Oceanographic Laboratory, Kochi, India

The Intel 80186 is a highly integrated 16-bit µP that is common to embedded applications. This µP's built-in interrupt controller has four interrupt-related pins that you can configure in various ways to achieve the maximum of four maskable interrupt-request lines.

In applications that require more than four interrupt- request lines, the only way out is to add an external interrupt controller, such as the 8259A. However, an alternative approach exists: You can through proper programming make the 80186's two timer-input pins function like normal edge-triggered interrupt request lines. The only penalty is an additional latency of about 1 µsec for an 8-MHz CPU, which is insignificant for many applications. This pseudo interrupt-request line is useful for interfacing any device (UART, DMA controller, coprocessor, or DSP processor) that works with internally vectored, edge-triggered interrupts.

The idea is based on the fact that you can program the timer in a mode during which the timer count resets and then the timer starts counting on a 0-to-1 transition on its input pin. Further, you can set the timer to interrupt when it reaches the value set in its Max Count register. Thus, if the Max Count setting equals 1, the timer generates an interrupt immediately after one timer-clock period from the 0-to-1 transition on the input pin. For an 8-MHz system, with the timer using the internal clock (which is one-fourth the CPU clock), the interrupt time is 500 nsec. The µP can serve the timer interrupt as any other normal interrupt would. The µP can also selectively mask and unmask the interrupt using the timer/interrupt-control registers.

A demo program demonstrates the use of the Timer0_In line as a pseudo interrupt-request line. The program, along with the setup in Figure 1 (which uses the Timer0_out line to generate the interrupt), also compares the latency of this pseudo interrupt with the latency of the normal interrupt line, Intr1. The program was written and compiled using Intel's IC86 compiler and was tested on an 8-MHz 80186 system. The same technique should work for µPs and µCs that have similar timer capabilities. (DI #2277)

DSP algorithm measures frequency and damping

Olga Belousova, Los Alamos, NM, and Alexander Belousov, New York, NY

The time-domain DSP algorithm described here allows you to measure the key parameters—natural frequency and damping—in linear, second-order electromechanical systems. The method applies to a range of electromechanical transducers (electromagnetic or electrostatic), including dynamic speakers, seismic geophones, micromachined sensors, and other systems. The algorithm is based on the integral transforms of the terminal voltage of the transducers in a free transient mode (after application and removal of the step-function stimulus). It provides high immunity to both electrical noise and mechanical vibration.

Compared with traditional FFT methods, the algorithm significantly simplifies the computational task, provides better resolution in locating the spectral peak (which corresponds with the natural resonant frequency of the transducer), and allows you to calculate the damping coefficient (which you can not directly extract from an FFT). Figure 1 uses an electromagnetic transducer, stimulated by a step-current function, with sequential integration of its terminal voltage in a free transient mode. The general equation (assuming zero initial phase) is:

where V_O is the final amplitude of the terminal voltage, b is the damping coefficient (an unknown value), and v₀ is the natural angular resonant frequency of the transducer system. The algorithm is based on the following integral transforms of the terminal voltage, v(t):

Omitting the intermediate math, you can write the computational formulas for b and v₀ as

For a practical implementation in DSP form, you must substitute the indefinite integrals J₁ through J₃ with corresponding finite sums S₁ through S₃. The ADC must digitize the terminal voltage during a period of time long enough to allow the free transient to settle. Then, the DSP must calculate the three finite sums using the following equations:

The final computational formulas are as follows:

where Dt is the sampling period.

The circuit in Figure 1 consists of the transducer under test, shown as inductor L_C in series with the coil resistance, R_C; a current-stimulus circuit (analog switch S with a current-limiting resistor, R_S, and the integrated ADC. We chose the low-power 10831 ADC from National Semiconductor (www.national.com) because of its convenient serial interface to the µC. Zener diodes D₁ and D₂ (approximately 5V breakdown) protect the ADC's input against overvoltage from inductive spikes).

The principal of operation is simple. First, you apply the current step function to the transducer. The duration of the current stimulus should be long enough to allow the transient to settle; this value depends on the estimated natural frequency and damping in the system. For example, for a typical seismic geophone with f₀=10 Hz and b=0.6, the step function should last 0.5 to 1 sec. The same rule applies to the measuring cycle in a free transient. In general, you can stop the measurement when the terminal voltage drops to less than 1 LSB in the chosen ADC. The sampling period, Dt, should be small enough to avoid methodical errors that accrue from substituting the analog integral transforms with discrete sums.

Because the resonant frequencies of mechanical systems are typically low, it is relatively easy to avoid the methodical errors. For example, the maximum sampling rate of the ADC 10831 is 74 kHz; thus, the resulting errors are low. You could also use a 10-bit 10732 ADC, a differential-input, single-supply device. For higher frequency and better resolution, you could use a 12-bit 12130 ADC, which has 14-µsec throughput time. You can use any embedded-system µC for the method. (DI #2244)

Video equalizer sharpens VCR images

Wayne Sward, Consultant, Bountiful, UT

Video signals from a VCR lose sharpness, resulting in a flat-looking image. The effect is especially noticeable when copying from one tape to another, as you do in a video-editing system. High-quality recorders minimize this effect, but they are expensive.

The circuit in Figure 1 sharpens picture images without introducing the shadows, ringing, and noise often observed with commercial video equalizers. The key to this improvement is the coaxial delay line, which replaces the typical LC network in other equalizers.

The circuit applies the video signal to a MAX466 quad video amplifier. The first amplifier drives a sample of the original video into a resistive summing network and a second amplifier through a 3.58-MHz trap. The trap deletes the chrominance-color signal from the original video. The second amplifier applies the remaining luminance-brightness video signal to the shorted coaxial delay line. This amplifier also applies a sample of the luminance signal to the resistive summing network. The total round-trip delay of the delay line is 65 nsec, about half the typical rise time of a VCR output for typical VHS or 8-mm VCRs.

The output of this delay line drives a third video amplifier, which recovers the edges of picture images. The enhanced-edge output of this third amplifier combines some of the original video signal from the first amplifier, some of the luminance video signal from the second amplifier, and the enhanced-edge video signal from the third amplifier into an improved video signal.

The 1N914 diode and associated resistors clip the video to -0.3V, which differentiates the enhanced video from being confused with normal sync signals. The resulting video signal drives one input of the fourth video amplifier. The second input of the fourth video amplifier is the original video signal, including sync and color burst. The LM1881 video- sync detector and the 74HCT30 NAND gate-switch this fourth video amplifier so that the original sync and color burst from the first amplifier go directly to the output, and the enhanced video signal from the summing network goes to the output during active video time.

The 680-pF capacitor across the video output suppresses switching transients generated in the fourth amplifier when switching between sync/color burst and enhanced video but does not degrade the enhanced video. The circuit also contains a power LED, a vertical-sync-indicator LED, and a bypass/boost switch. The power supply is a conventional linear design. The circuit is built on a double-sided copper-clad pc board.(DI #2251)

Programmable charger fills capacitor banks

Dennis Feucht, Innovatia Labs, Townville, PA

Designed for the use with a pyrotechnic pulse generator, the charger in Figure 1 uses low-cost components to charge the C₁ capacitor bank to a voltage as high as 75V, or to 25V in a few seconds. A 555 timer, IC₁, controls a flyback converter via the Q₁ transistor switch. The converter draws its charging current from a 5V supply. The 555 turns Q₁ on until T₁'s primary current reaches approximately 3A, as detected by comparator IC_2A, which turns IC₁ off. Then, Q₂ also turns off, and C₂ charges through R₁ and R₂, thereby setting the off-time of the charger cycle. IC_2D starts the new cycle by triggering IC₁.

Because R₁ connects to the charger output (V_C), as C₁ charges, the off-time decreases. The secondary conduction time decreases as V_C opposes T₁'s flux. But the flyback converter transfers no charge when T₁ is not conducting current. To minimize this no-charge time, the off-time decreases with V_C. R₂ is necessary for start-up, when V_C is 0V and cannot charge C₂. A digital input (charge) turns the charger on and off.

The target voltage on C₁ depends on the duty cycle of a 5V CMOS-level pulse applied to the PWM input. A 5-kHz PWM waveform has a scale factor of 0.75V/%. A 100% duty cycle produces a 75V target voltage. IC_2C detects when this voltage is reached and turns the charger off through D₁. IC_2C's output (Charged) can also indicate the completion of charging. If you use this output as a computer input, you should monitor it in a loop, because it is unasserted during recharge. R₃ provides hysteresis, and, as C₁ leaks charge and V_C decreases, IC_2C changes output state and charging commences, to keep C₁ "topped off." (DI #2260).

µC provides wireless keypad control

Lloyd Khuc, Motorola Inc, Austin, TX

The circuit in Figure 1 is a simple, 4X4 keypad remote-control system. A 68HC705J1A µC, IC₁ (Figure 1a), costs less than $1 and controls the keypad functions. When you depress any key, the µC provides a 4-bit hex-data output and then enables a latch signal to latch the data into IC₂. Next, the µC enables IC₂ to transmit the signal to the IC₃ encoder to convert the 4-bit hex data to serial data to send to IC₄. IC₄, the RF data-transmitter module, mixes the serial data with the 315-MHz carrier frequency to transmit.

In the receiver circuit (Figure 1b), the IC₅ data-receiver module removes the 315-MHz carrier frequency from the receiver signal, and IC₆ decodes the serial data into a 4-bit hex parallel data output. IC₇ converts the 4-bit hex data into 16 data bits to control 16 application circuits. IC₃ and IC₆ are a matching encoder/decoder pair that eliminates any unwanted interference frequencies. IC₄ and IC₅ are a matching RF data-transmitter/receiver pair with a 315-MHz carrier frequency. You can download the assembler code for the µC system by clicking here. (DI #2261).

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