October 8, 1998

Back to the breadboard

Graham Prophet, EDN Europe Editor

Once, a long time ago, logic design was straightforward. You wrote out your truth tables, drew your maps, worked out your Boolean equations, did a bit of minimisation, and pretty soon you were ready to reach for the orange book of MSI TTL functions. Before long, you had a rough cut of the function you wanted, soldered (or wire wrapped) together on the bench in front of you. An indeterminate amount of time later (the length of time often depending on how good you were with the fast oscilloscopes of the day), you had most of the bugs worked out of the design, and the next version of what usually turned out to be an extended family of prototypes was under way.

Then things started to get complicated. Designs became more and more complex, designers began to use simulation in a meaningful way, and methodology changed. The EDA business started to sell the concept that the whole design should be carried out in the "virtual" environment of the simulator, that there should be only a few prototypes (or even just one), and that the first specimen you built should be, for all practical purposes, identical with the first production unit.

Today, both ASIC and, albeit recently, FPGA vendors offer devices with very large gate counts that demand the importation of substantial blocks of intellectual property to fill them within a reasonable time. At the same time, new design methodologies struggle to keep up; gate-level simulation has faltered, faced with the scale of the full system simulations that replaced the old prototyping methods; and techniques such as cycle simulation and formal verification have come on rapidly to try to fill the gap.

Now, here's a curious thing: ASIC vendor VLSI Technology has introduced Velocity, a design flow that aims at addressing the shortcomings of today's tools when faced with today's development schedules. And what is a key element of this approach to cutting the design cycle? Hardware. As a cornerstone of Velocity, VLSI has built a library of bonded-out chips of its most used IP functions. At the same time, you can use the same standard buses on chip (PCI, for example) that you would use at the system level. There's a lot more to Velocity's approach than that; it is very much a language-based flow that appears to use the latest incremental synthesis techniques to optimise elements from the stock parts library to the precise feature mix that you want.

Still, this situation means you can check out major segments of your embryonic ASIC design by building them—and building them quickly. VLSI probably won't thank me for using the word, but it looks a lot like the breadboard is back, which begs the question, did it ever really go away?

I don't think it did. Even in an era in which prototyping a complete system has become impractical, we still explore critical circuit functions in hardware. HP and Tektronix (and others) continue building better logic analysers; these analysers' uses are not confined to the system-integration phase. And one of the benefits of design reuse is that some of the confidence you get from having hardware working on the bench you inherit with the reused elements. Also, I suspect that, in more organisations than might care to admit it, there's still an element in management that looks over your shoulder and says, "Yes, I'm sure the simulation is running beautifully, but don't you have something you can show me?"

You can reach EDN Europe Editor Graham Prophet at +44-118-935-1650, fax +44-118-935-1670, or graham.prophet@rbi.co.uk.

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