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EDN accepts nominations for 1998 Innovation AwardsNominate innovative people on your staff or an exciting product you've introduced over the past year for an EDN Innovation or Innovator of the Year Award. EDN's annual Innovation Awards recognize and spotlight excellence and creativity. The Innovator of the Year Award recognizes individuals and groups for innovation in design and technology. The Innovation of the Year Award recognizes unique, state-of-the-art electronics products in nine product categories: digital ICs; analog ICs and discrete semiconductors; microprocessors; test and measurement; EDA tools; computers, boards, buses, and peripherals; components, hardware, and interconnect; embedded development tools; and power sources and controllers. You can nominate any products or technologies introduced and commercially marketed from Jan 1, 1998, through Dec 31, 1998. EDN's technical editors will select the finalists, and you select the winners by voting on this Web site in February and March. Both the magazine and the Web site will announce winners in May 1999. Deadline for entries is Nov 13, 1998. To order a nomination packet, contact Kathy Leonard at 1-617-558-4405, kathy.leonard@edn.cahners.com, or Lynne M Guimond at 1-617-558-4590, Lguimond@cahners.com. |
Version 4.5 of Rapid Plus, a development tool for system man-machine-interface development, adds the ability to generate code that you can use in production versions of a design. Emultek wrote the original Rapid, a simulation and modelling package for man-machine interfaces. With the package, you model a proposed design in terms of the front-panel objectsand their expected behaviourthat the eventual user will see. The principle is process simulation rather than using a formal specification language. Marketing and engineering departments can, say the systems developers, come to an agreement on how the product should respond, and then embody this response in an executable form. The representation is state-diagram-based, and you define the model in terms of modes of response and the actions to get from one mode to the next. You can then use Rapid Plus for a variety of concurrent engineering tasks, such as test generation, documentation, training, marketing, sales-tool development, and code generation.
The software outputs C code for the man-machine interface, and a Rapid kernel runs on a variety of target µPs with links to popular real-time OSs. Emultek estimates that the overhead for using hand-crafted code is no more than 10 to 15% in a project of 100,000 lines of code. You can use a customised interface layer between the Rapid code running the man-machine interface and the remainder of the embedded-system software. This system outputs state diagrams; design occurs at a higher hierarchical level, according to Westland System Assessment, the UK agent for Emultek. The company also notes that it will keep code size in line with design complexity and that the Rapid environment can handle concurrent modes.
Westland is also the UK source of the Care software package from BQR Reliability Engineering. Care forecasts the reliability and maintainability of a product on an analytical and statistical basis. Intended as a design tool for hardware engineers and test engineers, it can access a variety of CAD and EDA database formats and has links to simulation tools, including Spice. It forecasts MTBF and component stress and, if a thermal-analysis package is lacking, performs a first-order thermal analysis to predict device temperatures. It includes modules for reliability planning; testability analysis; and whole-life product management, including scheduling maintenance and providing spares. By providing a means of whole-life costs, it lets you address increasingly important design-for-end-of-life issues.
Emultek, Jerusalem, Israel, +972 2 587 0770, www.emultek.com.
BQR Reliability Engineering, Rishon-LeZion, Israel, +972 3 966 3569, www.bqr.com.
Westland System Assessment, Yeovil, UK, +44 1935 401100, www.gkn-wsal.com (United Kingdom only).
Until now, designers have associated chip-scale packaging and formats such as µBGA with high-pin-count devices; now, Xicor has created the Xicor BGA (XBGA), which packages die with as few as eight pins. EEPROMs packaged in this technology have a footprint essentially the same as that of the die. The assembly procedure for the package starts with a thin glass wafer, which the manufacturer bonds to the front of the die. Xicor then laps down the silicon wafer to reduce its thickness, a standard operation for low-profile packages, separating the die by etching rather than sawing. The company then bonds a second glass wafer to sandwich the silicon, cuts the front-side glass layer to expose the aluminium connections of the die, deposits more aluminium to bring the connections to the top of the front-glass layer, and then applies solder bumps to that layer. Xicor then separates the die; sealing is inherent in the process, and the process uses no epoxy overmould. You can buy 64- and 128-kbit EEPROMs in the 0.5-mm-thick package for $1.70 to $2.95 (10,000), depending on density and serial interface.
Last year, Toshiba and Fujitsu introduced a BGA multichip package that placed flash and SRAM die side by side in one package measuring about 1 cm per side, which the two companies say has found good acceptance in cellular-phone designs. As a derivative of that technology and with the added participation of NEC, the companies are defining a new format that will stack the two die to further reduce footprint. The two die are one NOR-type 4- to 128-Mbit flash and one 1- to 16-Mbit SRAM in various combinations. The format defines an 8X8-ball layout on a 0.8-mm pitch using 56 positions; the format is pin-compatible with all combinations of memory, and a pin provides switching between 38 and 316 outputs. The format requires 70% less area than two TSOPs. Samsung, Seiko Epson, and Hyundai also support the format, and samples should be available by year-end.
IBM has also announced new formats for high-integration ASICs and systems. The company uses ultra-fine-pitch wire-bond plastic BGAs to reduce die pitches to less than 60 mm for higher I/O counts and densities of more than 1000 I/Os. A second technique, glass-ceramic chip carrier, addresses footprint, thermal, and electrical issues; it eliminates thin films from the glass ceramic for cost reasons and, by matching substrate and silicon thermal characteristics, handles very large die for 5000 interconnects on the package and more than 1600 connections off the package. The technique uses the C4 flip-chip die-attachment technology. IBM is also employing a multichip-module (MCM) technology that uses a laminate substrate, providing MCMs usual density and performance gains and controlling costs.
And, how do you connect your very-high-pin-count IC to a board if you want a removable device? Thomas and Betts offers a new interconnection system for that need. The company based the system on metallised particles embedded in polymer. The system allows you to connect packages with more than 1000 I/Os. Metallised-particle interconnect shapes the metal particles into tiny columns within a flexible polymer carrier in the socket. The technique achieves reliable connection at a force of 50 gm per contact, managing the forces for a complete, very large device. The system provides 1000 mating cycles and 0.2-nH mutual inductance between columns.
Xicor, Witney, UK, +44 1993 700544, www.xicor.com.
Toshiba Europe, Dusseldorf, Germany, +49 211 52 960, www.toshiba.com.
IBM Microelectronics, Paris, France, +33 1 60 88 55 64, www.chips.ibm.com.
Thomas and Betts, Rhode-St-Genese, Belgium, +32 2 359 8300, www.tnb.com.
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