October 8, 1998
Analyze the cause of signal jitter in passive structures
Signal jitter in passive interconnections, such as connectors and pc
boards, can be a significant source of error in a high-speed digital system. Simulation
results illustrate how adjacent signals induce jitter by producing impedance changes in
the active line. Simple grounding guidelines help you minimize the problem.
Chad W Morgan And Hank Herrmann, Amp Inc
As data rates increase and digital rise times grow steadily shorter in high-speed
digital systems, it becomes increasingly important to pre-serve signal integrity in logic
design. To ensure proper timing in a high-speed system, the design phase of any digital
system must account for phenomena such as signal skew and data jitter. Following a few
simple design guidelines, you can prevent system errors that result from excessive signal
skew and jitter.
System designers most commonly associate jitter with digital-driver imperfections. For
example, jitter can result when a driver amplifies thermal noise at its input. To help
alleviate this problem, a device's technical data sheets usually provide maximum-jitter
specifications, typically consisting of minimum and maximum pulse widths, clock periods,
setup times, and hold times. This type of information allows a system designer to
compensate for this type of error in a new system design.
Unfortunately, system designers do not often fully consider the jitter element that
high-speed signals can induce in a passive interconnect. Designers usually attribute this
type of jitter to crosstalk. However, to truly explain induced signal jitter in passive
structures, you must examine the changing effective impedance of a structure with regard
to its boundary conditions at any given time. The effective impedance of a structure is a
dynamic property that is not based solely on geometry and materials.
Examine the effective impedance
Consider the example structure in Figure 1a, which
contains two inner signal conductors and two outer return paths. Assuming that the
structure is lossless, you can represent this structure with the lumped element model in Figure 1b, which includes near-end drivers, ground
connections, and far-end terminations.
Assume that the driver impedances and the far-end termination impedances in Figure 1b are 50 Ohm. Further, assume that the nominal
impedance of a signal line (the impedance of the line when all surrounding lines are
static) is 50 Ohm. When the system drives only one of the signal lines at a high
frequency, the active line has a matched impedance. In this case, the signal travels
smoothly down the line without signal reflections, as Trace B in Figure 2 depicts.
If, however, two synchronous, in-phase signals travel down the two signal lines in Figure 1a, the effective impedance of each signal line is
more than 50 Ohm. To understand why the effective impedance rises on each line, examine
the circuit components in Figure 1b. The effective
impedance (ZEFF) of each signal line is as follows:
The incremental effective capacitance (CEFF) is the capacitance of the
appropriate parallel combination of CM and CG. Equally exciting both
signal lines eliminates displacement current between signal lines, which eliminates the
effect of the capacitance between the lines. Only the capacitance to ground remains. The
total effective capacitance is reduced, thus raising the effective impedance of each
driven line.
The incremental effective inductance (LEFF) also changes. The value of LEFF
results from a complicated interaction between the partial inductance along with the
conductors (LS) and the mutual inductance between them (LM). When
only one line is active, current returns in all other lines, and all mutual inductances
subtract from the partial series inductance in proportion to the magnitude of the induced
currents. When two lines are active, the mutual term for the second signal line adds to
the total, LEFF. Again, the effect of the mutual inductances are proportional
to the magnitude of the induced currents, so that LEFF changes but not by a
simple factor of 2LM.
Once you understand that the applied signals dynamically change the effective
impedance, you can easily understand the reason for the jitter. Because the results are
the same as those that occur in any mismatched situation nothing unexpected occurs (Figure 2). Trace B shows nice digital waveforms traveling down
a line with matched impedances. The Trace A waveforms show the expected response at the
near and far ends (figures 2a and b, respectively) of a
line that has a higher impedance than the source and the load, because the surrounding
signals are rising. Trace C waveforms show the expected response when a line has a lower
impedance, because the surrounding signals are falling.
The timing changes arise because, when the signal has different amplitudes, it crosses
the threshold at different times. The effective impedance changes in response to the data
signals in the structure and complicates the effects of coupled passive structures. Figure 2 shows the first incident condition for a long
structure.
At the near end of the structure and in response to rising surrounding signals, the
waveform shifts to a point earlier than when only one signal line is active—from
Position B to Position A (Figure 2a). This shift occurs
when the first incident waveform to the transmission line reaches higher values more
quickly than it does when only one line is active. This effect results from the
high-frequency voltage divider between the 50 Ohm driver impedance and the transmission
line's higher effective impedance.
At the far end of the structure and in response to rising surrounding signals, the
waveform shifts to a point later than than when only one signal line is active—again
from Position B to Position A (Figure 2b). The far-end
shift is directly related to the reflections that occur at the end of the line because of
the impedance mismatch between the transmission-line structure (with an effective
impedance of more than 50 Ohm) and the far-end 50 Ohm termination resistor. The higher
line impedance causes a negative reflection at the far end such that the instantaneous
value of the far end waveform is
where VF is the far end voltage, and VN is the near end voltage
that has traveled to the end of the line. GL is the reflection coefficient at
the load, expressed as
where ZEFF is the effective impedance of the signal line and ZL
is the impedance of the far-end termination. The negative reflection at the far end adds
instantaneously to the far-end incident signal, resulting in a waveform that shifts down
in value. The signal appears then to arrive later.
Thus, in-phase synchronous signals can cause a time shift in an active signal at both
the near and far ends of a passive structure. Using similar logic, you can show that
nearby, synchronous signals that are exactly 180° out of phase can cause the opposite
time shifts. In other words, a nearby falling-edge signal induces a rising active signal
to cross a threshold later at the near end and earlier at the far end than when the active
signal has no active lines near it. The Trace C waveforms in Figure
2 illustrate this case.
Three passive structural types
Induced time shifts become significant in a real system with random digital-data
sequences traveling through many lines of interconnections and pc boards. Fortunately, you
can analyze signal jitter in simulated passive structures, such as open-pin-field and
microstrip structures. Understanding the results of simulation and analysis provides
guidelines that help you reduce signal jitter in system interconnections.
You can gain useful information by analyzing a 6-in.-long open pin field in a
three-to-one signal-to-ground ratio (for illustrative purposes only); a 1-in.-long open
pin field in a three-to-one signal-to-ground ratio, which is similar to a poorly
referenced board-to-board high-speed connector; and a 6-in.-long microstrip structure,
which represents the path a signal might take through a printed wiring board.
Proven computer-modeling techniques provide the data for each structure. The structure
models are created with Maxwell 2-D electromagnetic modeling software (Ansoft Corp, www.ansoft.com), and the simulation results are obtained
using HSpice (Meta-Software, www.metasw.com)
simulation of various circuits connected to the models. Figure
3 shows the circuit connections to the various lines in the models.
Structure 1: 6-in.-long open pin field
Figure 4 shows a 6-in.-long open pin field with seven
signal pins and two ground-return pins. Although excessive length and poor ground
referencing make this structure unrealistic for use in high-speed digital systems, it
serves as a good model for understanding how adjacent signals produce jitter on an active
signal in a passive structure.
Three simulations were performed on the structure in Figure
4. The first simulation drove Pin B2 high and kept the remaining pins quiet. The next
simulation drove Pin B2 high and drove the remaining signal pins high. The final
simulation drove Pin B2 high and drove the other signal pins low. Figures 5a and 6a show the
simulation data for the three scenarios. Figure 5b measures
the effective input impedance of Pin B2 when nearby signals swing high and when they swing
low. Figure 6b represents a separate simulation that
measures crosstalk (see sidebar "Correlate crosstalk with
impedance changes").
In figures 5a and 6a,
both the near- and far-end voltages on Pin B2 swing smoothly to the final value of 1.2V
when nearby signal lines are quiet. This situation results from the matched impedances of
the driver, the line, and the load.
When nearby signals go high, however, the rise in its effective impedance causes Pin
B2's waveform to shift dramatically. Figure 5b shows an
initial impedance on Pin B2 of approximately 135 Ohm when nearby signals are high. This
135 Ohm line impedance in series with the 50 Ohm driver impedance results in an expected
first-incident near-end voltage of
where VS and ZS are the source voltage and impedance,
respectively. This high-frequency voltage-divider prediction matches the actual measured
near-end voltage of 1.75V (Figure 5a). You can use the same
method to predict the downshift of input waveforms when surrounding lines are driven low.
The data indicates a significant change in the time a signal takes to cross a threshold
at the input to a passive structure. Nearby active signals change the line's effective
impedance, which in turn causes the time shift, or jitter. This data-dependent jitter can
either extend or reduce the trigger time. In a synchronous digital system with random data
sequences, the result is random signal jitter at the near end of a passive structure. Figure 5a shows that this jitter can be significant in a
structure that's poorly referenced to ground, such as the structure in Figure 4.
The near-end noise that signals induce in a passive structure can be of concern in a
bused system with near-end receivers. However, far-end jitter can affect both bused
systems and high-speed point-to-point systems. Figure 6a
shows the far-end waveforms for simulations of the 6-in. pin-field structure. The
simulation that drives the surrounding signals high causes the far-end waveform to shift
to a later point than when nearby signals are quiet. This shift occurs because of an
instantaneous reflection at the structure's far end caused by the impedance mismatch
between the line and the far-end termination. You can calculate the far-end reflection
coefficient as follows:
By knowing GL, you can calculate the first incident far-end voltage as
follows:
Figure 6a shows this predicted value equals the
approximate initial voltage level of Pin B2's waveform at the far end when nearby signals
are high. Figure 6a also shows the simulation that drives
nearby signals low and the resultant far-end shift to an earlier point.
The far-end incident voltage's shift in time is directly related to the reflections
that result from the impedance mismatch at the far end (Figure
6a). The mismatch itself results from the effective impedance change on the line
because of nearby signals. The remainder of the voltage steps results from ever-decreasing
voltage reflections at both the near and far ends of the line (figures
5a and 6a). In time, the line impedance returns to 50
Ohm, and reflections become negligible.
Structure 2: 1-in.-long pin field
In an electrically long structure, such as the 6-in.-long pin field, it is relatively
simple to analyze the physical phenomena that cause signal jitter in a passive structure.
However, analysis becomes more difficult in an electrically short structure, for which the
propagation delay of the line is less than or equal to the rise time of the signal. The
initial-voltage values and reflections now interact with one another during the
transition, and these values are not independently observable. A structure that
demonstrates this concept is the 1-in.-long pin field (Figure
7).
The structure in Figure 7 is typical of a
board-to-board connector that many high-speed systems use. Figures
8a and 9a show data for this structure under the same
simulation conditions as the 6-in. pin field.
You can perform an analysis similar to that performed on the 6-in. pin field for this
short structure. However, complicated time interactions of incident voltages and
reflections may make this analysis tedious. Perhaps the easiest way to examine the data of
figures 8a and 9a is to view
it as a time-compacted version of the data shown for the 6-in.-long openpin field.
Although the same phenomena occur in both the 1- and 6-in. structures, reflections in
the 1-in. structure interact with the edge of the active signal. As a result, the sharp
voltage steps in the 6-in. pin- field structure's waveforms appear as smooth transitions
in the 1-in. structure's waveforms. Further, in the 1-in. structure, signal reflections
interact with initial voltage swings to reduce maximum voltages.
The most important point to observe in figures 8a and 9a is that signal jitter can be significant in a real-world
structure. In this 1-in.-long pin field, jitter at 0.8V can be as large as 440 psec at the
near end and 300 psec at the far end. These magnitudes suggest that induced signal jitter
in passive structures is a significant source of error in high-speed system design.
To minimize induced signal jitter in a passive structure, you must keep the effective
impedance (ZEFF) of each signal line steady under all circumstances. The best
way to keep it steady is to ensure that signal lines are tightly coupled to ground and
weakly coupled to each other. This coupling keeps effective impedances more constant. If
the line is properly matched, reflections and first-incident-voltage shifts will be small
and thereby will reduce induced signal jitter within the structure.
Structure 3: 6-in. microstrip
Simulation data for the 6-in. microstrip structure (Figure
10) shows how strong grounding can eliminate induced signal jitter in passive
structures. In this geometry, an active high signal travels down Pin A. The simulation
monitors this active signal when the B pins are quiet, when they swing high, and when they
swing low.
The simulation results in figures 11a and 12a clearly show that nearby active lines in this structure
induce little jitter on a signal. At the near end, only 128 psec of jitter is observable,
and, at the far end, only 113 psec of jitter is present. For the 500-psec edge signal,
this signal jitter represents only 20% of the rise time. This jitter reduction results
directly from the strong grounding in the microstrip structure, which holds the effective
impedance of each signal line steady. Only a 12 Ohm impedance rise (from 50 to 62 Ohm) at
the input of the line occurs when nearby signals swing high (Figure
11b). This rise is much lower than the 85 Ohm rise from 50 Ohm in the simulations of
the 6-in.-long pin field.
The most important technique for reducing induced signal jitter in passive structures
is eliminating signal-to-signal coupling. You can eliminate this coupling by increasing
either signal-to-signal spacing or signal-to-ground coupling. Either of these methods
keeps effective line impedance steady and minimizes signal reflections. Note that you must
match the driver and termination impedances to the nominal line impedance at high
frequencies.
Simple guidelines help reduce jitter
The following design guidelines reduce interconnection signal jitter. Designers
commonly use these signal-integrity guidelines to promote positive signal behavior in
high-speed systems.
- Use well-grounded structures in pc boards, such as microstrip, stripline, and
dual-microstrip geometries.
- Keep high-speed parallel traces spaced as far apart as routing will allow.
- Keep parallel trace-to-trace spacing large, relative to trace-to-ground plane spacing.
- Assign numerous pins to ground when routing signals through an open-pin-field connector.
Aim for a 1-to-1 signal-to-ground ratio, if possible.
- Space ground pins evenly throughout an open-pin-field connector to maximize
signal-to-ground coupling.
- Choose high-speed connectors with 1-to-1 signal-to-ground-ratio impedance that matches
the impedance of system pc-board trace layers.
- For optimum performance, choose connectors with built-in ground planes, such as the Amp
HS3, Mictor, and Microstrip connectors.
Signal-integrity engineers commonly consider jitter as it relates to crosstalk. You can
correlate crosstalk data to the impedance studies presented in this article.
In Figure 6b, data from a separate simulation monitors
quiet Pin B2 when all surrounding signal pins switch high and then measures the induced
near- and far-end crosstalk. Figures 9b and 12b show the results of crosstalk simulations similar to those
that produce the values in Figure 6b.
Then, using the mathematical principle of superposition, you can add this measured
noise to Pin B2's waveform when nearby signals are quiet to derive the waveforms in both figures 5a and 6a for which
nearby signals are active.
The principle of superposition can be a useful mathematical tool because companies such
as Amp Inc provide crosstalk measurements for high-speed connectors. However, analyzing
the jitter purely from a crosstalk perspective does not help you understand why so many
reflections occur on seemingly matched lines. You can achieve proper insight by
considering the jitter from a changing-impedance perspective. |
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