10.22.98 Covering your HDL chip-design bets: Table 1

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October 22, 1998

Covering your HDL chip-design bets

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Table 1—Common code-coverage tool capabilities
General HDL coverage	VHDL/Verilog applicability	Descriptionaaaaaaaaaaaaaa	Design level			Summit Design	TransEDA	Advanced Technology Center	interHDL	Design Acceleration
General HDL coverage	VHDL/Verilog applicability	Descriptionaaaaaaaaaaaaaa	Behavioral	RTL	Gate	Summit Design	TransEDA	Advanced Technology Center	interHDL	Design Acceleration
Statement (block, line)	Both	Shows whether a simulation has executed an HDL statement	Yes	Yes		HDLScore	VHDLCover, VeriSure	CoverMeter	CoverIt	Coverscan/ Statescan
Branch	Both	Shows whether a simulation has executed conditional branches of IF or CASE statements	Yes	Yes		HDLScore	VHDLCover, VeriSure	CoverMeter	CoverIt	Coverscan/ Statescan
Condition (expression)	Both	Shows whether all input conditions to an IF or CASE statement have been executed	Yes	Yes		HDLScore	VHDLCover, VeriSure	CoverMeter		Coverscan/ Statescan
Toggle	Both	Shows which signal bits have changed state	Yes	Yes	Yes		VHDLCover, VeriSure	CoverMeter	CoverIt
Path	Both	Calculates sequential paths through IF and CASE statements	Yes	Yes		HDLScore	VHDLCover, VeriSure		CoverIt
Variable-trace coverage	Verilog	Shows how well specific variables, such as state variables or ROM addresses, have been tested with a range of values	Yes	Yes	Yes	HDLScore	VeriSure	CoverMeter	CoverIt	Coverscan/ Statescan
Signal-trace coverage	VHDL	Shows how well specific signals, such as state variables or ROM addresses, have been tested with a range of values	Yes	Yes	Yes		VHDLCover
Triggering	VHDL	Shows whether one of the signals in the process' sensitivity list has uniquely triggered each process	Yes	Yes			VHDLCover
State-machine coverage
State visitation	Both	Shows whether a valid state has been reached				HDLScore	StateSure	CoverMeter	CoverIt	Coverscan/ Statescan
Arc (transition)	Both	Shows whether a state transition has occurred				HDLScore	StateSure	CoverMeter	CoverIt	Coverscan/ Statescan
Expression	Both	Shows whether the expressions controlling a state transition have been fully tested				HDLScore	StateSure	CoverMeter		Coverscan/ Statescan
Sequence	Both	Shows whether specific state sequences have been tested				HDLScore	StateSure		CoverIt	Coverscan/ Statescan
Pair arc	Both	Shows whether a pair of state machines has simultaneously executed specific transitions					StateSure			Coverscan/ Statescan
Pair and sequence combinations	Both	Shows which complex multiple state-machine interactions have been tested					StateSure

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