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Covering your HDL chip-design
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Table 2—Representative
EDA-vendor tools for code-enhancement and -coverage analysis
|
| Company |
Product |
Function |
Verilog or VHDLaaaaa |
Abstraction level |
Unix or Windows |
Starting price |
| Advanced Technology Center |
CoverMeter |
Test coverage analysis |
Verilog |
Behavioral, RTL, gate |
Unix |
$10,000 |
| Design Acceleration |
DAI Coverscan/ Statescan |
Test coverage analysis with state-machine
extraction |
Verilog |
RTL |
Unix |
$15,000 |
| interHDL |
Verilint |
Semantics, synthesis, and coding style checker |
Verilog |
RTL |
Both |
$9500 |
| VHDLlint |
Semantics, synthesis, and coding style checker |
VHDL |
RTL |
Both |
$9500 |
| Checkit |
Clock-domain analysis and asynchronous-loop identification |
Both |
RTL, gate |
Both |
$20,900 |
| Testit |
Testability analysis |
Both |
RTL, gate |
Both |
$20,900 |
| Coverit |
Test coverage analysis with power profiling |
Verilog |
RTL, gate |
Both |
$14,900 |
| Quickturn Design Systems |
StyleCheck |
Syntax and design-rule checking |
Verilog |
RTL |
Both |
$28,000 |
| Summit Design |
HDLScore |
Test coverage analysis with state-machine extraction |
Verilog |
Behavioral, RTL, gate |
Unix |
$22,000 |
| SynTest Technologies
|
TurboCheck-RTL |
Testability analysis |
Verilog |
RTL |
Both |
$20,000 |
| FCE-RTL |
Fault-coverage enhancer |
Verilog |
RTL |
Both |
$10,000 |
| TurboFault |
Fault grading |
Both |
Gate |
Unix |
$50,000 |
| TransEDA
|
VHDLCover |
Test coverage analysis |
VHDL |
Behavioral, RTL, gate |
Both |
$20,000 |
| VeriSure |
Test coverage analysis |
Verilog |
Behavioral, RTL, gate |
Both |
$20,000 |
| CoverPlus |
Regression suite optimization |
Both |
RTL, gate |
Both |
$25,000 |
| StateSure |
Finite-state-machine verification |
Both |
Behavioral, RTL |
Both |
$25,000 |
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