Clock drivers ensure on-time arrival of high-speed signals

Programmable-skew PLL-based clock drivers can operate as true multifunction devices. Some can divide, multiply, invert phases, and adjust phases while maintaining exceptionally low output skew.

Dan Andersen, Quality Semiconductor Inc

As system-clock speeds rise to the 66- to 100-MHz range, designers need to distribute clock signals in an orchestrated manner among various devices on a pc board. A clock signal that arrives too soon or too late to one device not only impairs its combined performance with other components, but also degrades overall system performance. In high-performance applications, such as synchronized computing, telecommunications, networking, and portable-communications systems, proper distribution and timing become increasingly important because you need to distribute faster signals more precisely.

Achieving clean and precise clock-signal distribution requires dealing with many issues, such as compensating for differences in trace delays from one load to the next and equalizing the differences in setup and hold times among various devices. These issues boil down to skew—the gap between when a clock signal is supposed to arrive at a device and when it actually does. When cycle times are approximately 50 nsec, you do not have to worry too much about skew because it is not a major factor in total cycle time. However, as cycle times drop to 15 nsec or lower, managing skew becomes increasingly critical because high-speed systems can allocate only approximately 10% of the total timing budget to skew. For these systems, minimizing skew is necessary for optimum system performance.

SKEW COMES IN TWO FORMS

To complicate things, skew comes in two forms: clock-driver-induced skew and pc-board-layout-generated skew. Clock-driver skew is inherent within the operation of the clock-driver circuitry itself. Board-design skew depends on a combination of factors, such as the length of the traces, capacitive loading of those traces, variations in threshold voltages, and transmission-line terminations. Fortunately, you can calculate these two forms of skew and use the results to program delivery of signals to devices to compensate for skew. This programming is somewhat analogous to having a relay runner leave his position early to receive a baton on time at full speed.

Fortunately, high-performance, programmable-skew clock drivers that integrate as many as eight outputs are now available. These devices more precisely distribute several signals within high-performance computing applications, such as Pentium- or RISC-processor-based systems. These clock drivers are also becoming important in networking systems, such as Fast Ethernet, asynchronous transfer mode, and base stations for Global Systems for Mobile communications/personal-communications service. The devices compensate for variations in trace delays and equalize differences among devices during mismatches in setup-and-hold times.

Programmable-skew clock drivers ideally suit a variety of applications, including generating a synchronous clock for multiple processors, implementing PWM, overcoming timing violations (Figure 1), operating as a universal clock multiplier, and serving as a continuously phase-adjusted clock source. You can also cascade the devices to create multiple sets of programmable clock skew.

Because these programmable clock- driver devices are so versatile, you can base your selection on a variety of features, including skew and jitter timing specifications; output-level specifications; divide, multiply, and phase-adjust features; programmable timing flexibility; frequency range; power consumption; power-supply voltages; and size.

To select the proper clock driver, you need to ask a number of questions that relate to these features. For example, are skew and jitter low enough, such as less than 200 psec, for the optimum perform-ance of your system? You may also need to know whether the multiple outputs are compatible with CMOS, TTL, and low-voltage-TTL levels. Is it necessary to phase-adjust, invert, multiply, or divide the outputs? Can you program the output delays for durations (as long as 18 nsec, for example) and intervals (750 psec to 1.5 nsec, for example) among the multiple outputs to suit your application? Does the clock driver have a synchronous output enable to ease the testing of traces on system boards? Is the frequency range wide enough, such as 100 MHz? Is power consumption low enough, such as in a CMOS device? Can you use either 5 or 3.3V power supplies? Is the package style appropriate?

Another feature these new devices provide is more flexibility; you can use one device to synchronize output signals with either the positive (rising) or negative (falling) edge of the system clock. This selectable positive- or negative-edge synchronization means that you can more easily work with devices that run on negative clock edges, such as DSPs. Also, an on-chip loop filter, which can help maintain low jitter, saves space by eliminating five to eight external components.

BUFFER AND FEEDBACK DRIVERS

Programmable clock drivers are available in buffer- and feedback-type architectures. Buffer-type clock drivers propagate the input waveform through the device so that the output signal directly matches the input signal, often generating as many as eight output signals of the same strength. The output skew depends on variations in the propagation delay of the input signal through the device and on how finely matched the device's internal circuitry is.

The 74F244, which several manufacturers offer, is an example of a buffer-type clock driver. This IC has eight inputs that directly drive their matched outputs. Tying the inputs together turns the IC into a clock-distribution chip, which lessens the addition of input skew to the inherent device skew.

Unfortunately, although manufacturers offer buffer-type clock drivers with output skew as low as around 500 psec, these devices still have problems with internal propagation delay through the device. The internal propagation delay can be as high as 3 nsec, creating skew in systems that need to synchronize the reference clock to the buffer and the buffer outputs. A 3-nsec clock-driver skew may be acceptable for the design and board layout of 20- to 25-MHz systems, but such skew becomes increasingly unacceptable as system clock rates increase.

Also, you cannot frequency- or phase-adjust the outputs of these buffer-type devices. Adjusting the frequency enables the distribution of low- and high-frequency clocks from the same common source. Phase adjustment is important because it permits the clock driver to adjust for mismatches in trace propagation delays and differences in setup-and-hold times. Another issue with these devices is that the output waveform is directly tied to the input waveform. In a form of garbage in, garbage out, a less-than-ideal input creates a suboptimal output. You can deal with these two problems but with the added cost of using expensive external components, such as crystal oscillators. Furthermore, correcting these problems requires additional board routing, which lengthens and complicates design time.

FEEDBACK PROVIDES FLEXIBILITY

Feedback-style programmable clock drivers have none of the problems that buffer-type drivers have, and they provide flexibility and efficiency. Based on PLL designs, these devices use a feedback input that is a function of one of the outputs. PLL techniques square the reference input with the frequency and phase of the feedback input, which makes possible an accurate prediction of the next output signal and practically eliminates internal propagation delay through the device. Moreover, PLL-based feedback architectures permit you to selectively divide, multiply, and invert outputs with very low output skew.

You can also phase-adjust the output signals to compensate for both trace-length mismatches on the pc board (Figure 2) and backplane propagation delays and to handle special timing relationships among clocked components. Adjusting the phase permits outputs to shift in time relative to a reference point—usually the input clock. Phase shifting not only compensates for differences in trace delays between loads, but also equalizes the differences in setup-and-hold times between loads. These features provide programmable skew that enables outputs to lead or lag behind the reference-input signal.

The architecture of one programmable-skew PLL clock driver includes eight programmable-skew outputs in four banks of two, with each bank connected to a function-select (nF1:0) input (Figure 3). A skew-select block controls each bank pair, responding to a single PLL that monitors the frequency-select (FS), reference-input (REF), and feedback-output (FB) signals. Skew comes in 250-, 500-, and 750-psec specifications. Typically, you can select skew timing in multiples of a time unit, t_U, which is usually about 1 nsec. Each bank pair has nine skew-timing choices, including zero skew, which you choose using the control pins.

To minimize the number of control pins, the device uses three-level inputs (high, mid, and low) for—but not restricted to—hard wiring. The three-level inputs create the leading, lagging, and dividing functions for each output pair (Table 1). Table 2 shows the PLL's programmable-skew range and resolution based on low, mid, and high settings. These three-level inputs also keep I/O count to easily managed 28- and 32-pin PLCC or SOIC packages.

The integrated PLL in this clock driver comprises a phase detector to gauge the phase and frequency of the input signals, a loop filter, and a VCO. Designers choose an FB signal to feed back to a REF signal that the driver uses to adjust all other outputs. During operation, the phase detector compares the rising edge of the REF signal with the FB signal to determine whether the two are in sync. If the reference input precedes the FB signal, the phase detector speeds up the VCO until the FB signal catches up with the REF signal. The phase detector slows the VCO if the reverse condition occurs. If no REF exists, the device runs at its lowest operating speed. The internal loop filter transforms the signals into one control voltage, and the number of prior speedup and slowdown pulses determines the range of this voltage. The voltage range that the filter produces keeps the VCO within the selected frequency range.

MAKE A MULTIFUNCTION CLOCK DRIVER

Designing with a programmable-skew PLL clock driver makes it easy to implement a variety of functions. These functions include programmable phase adjustment, frequency multiplication, frequency division, frequency division and multiplication, low-skew clock buffering, inverted-output clock driving, and multifunction clock driving (Figure 4).

For a programmable phase-adjustment function, for example, you can configure the clock driver to phase-shift the 3Q outputs so they lag the reference input while phase-shifting the 4Q outputs so they lead the reference input. For a frequency-multiplier function, choose an output that divides by two or four for the FB input. For a frequency-divider function, with the PLL running at 20 MHz, tie the FS input to ground to select a 15- to 30-MHz operating range. Then, you can easily connect the appropriate output to the FB pin to divide by two or four.

PUT CLOCK DRIVERS TO MANY USES

Configuring the PLL clock driver as a low-skew clock buffer is relatively easy. You simply leave all the function-select inputs open or unconnected and take the FB input from any output. However, using the shortest connection, either from the 1Q or 2Q outputs, produces the best perform-ance. The shortest wire should mitigate the effects of stub reflections on the clock line connected to the input and the output used for the FB input.

A PLL clock driver also can act as an inverted-output clock driver. This configuration serves system designers who must deal with a large number of clocks that are inverted or phase-shifted by 180°. You can clock the logic at twice the frequency without unsettling a higher frequency clock. You can configure the clock driver so that all outputs have 180° of phase shift. The device can also divide the frequency by two or four while remaining in inverted mode, even as other outputs are phase-shifted. If you need only two inverted clocks, you can configure the driver to phase-invert two outputs without affecting the other outputs.

Finally, you can cascade programmable-skew PLL clock drivers to create more clock outputs. Also, these devices can drive external devices, such as buffers, frequency dividers, and multipliers placed between one of their outputs and the FB. This setup requires, however, that the FB input is a function of the outputs, and you must account for the skew and delays of the external devices.

Author's biography

Dan Andersen is the director of corporate communications for Quality Semiconductor Inc (www.qualitysemi.com). He holds a BS in business management from Golden Gate University (San Francisco).

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