FPGA/DSP-development kit features RTL and model-based support
Rick Nelson, Editor-in-Chief -- EDN, April 22, 2010
The Avnet Electronics Marketing operating group of Avnet Inc is now accepting orders for its $1995 Xilinx Spartan-6 FPGA/DSP-development kit. The kit includes a device-locked version of Xilinx’s ISE (integrated software environment) Design Suite System Edition 11.4. Each Spartan-6 FPGA achieves as many as 45 billion MAC (multiply/accumulate) operations/sec to serve computationally intensive applications that demand high digital-signal-processing performance at low cost. The new kit represents a DSP-domain-specific extension of Avnet’s Spartan-6 FPGA evaluation and development kits that the company introduced last fall.
“With the introduction of the Spartan-6 FPGA DSP kit, Avnet is offering its first DSP-development platform for customers who need greater performance and low cost,” says Jim Beneke, vice president for global technical marketing at Avnet Electronics Marketing. “This kit will help our customers quickly learn the tool flows and design techniques involved in creating DSP-centric designs with Spartan-6 FPGA.”
The development kit combines a scalable development board, DSP IP (intellectual property), DSP-development tools, and a preconfigured and fully validated Spartan-6-DSP-targeted reference design. This design serves as a basis for illustrating DSP techniques and design flows for the Spartan-6 class of signal-processing functions.
The kit includes both RTL (register-transfer-level) and model-based design support. Its model-based design flow uses The MathWorks’ Matlab and Simulink to allow algorithm developers to create DSP-hardware designs using a familiar modeling environment without the need to learn RTL. For experienced RTL designers, the kit supports design techniques for creating efficient DSP hardware using ISE Design Suite and LogicCore DSP IP along with verification methods for comparing functional correctness against high-level algorithm models.
The reference design includes design-source files for RTL and Simulink, top-level system-integration RTL source files, a simulation environment, test benches, an implementation environment, place-and-route and timing-closure support, and tutorials highlighting recommended flows for design modification and integration.
“Model-based design using Simulink eases the adoption of FPGAs and significantly accelerates FPGA implementation of signal-processing, computer-vision, and control-system applications,” says Amnon Gai, a manager in The MathWorks’ corporate-development and partner-programs group. “With Xilinx System Generator, it provides a turnkey rapid prototyping solution for engineers new to FPGAs without RTL design experience.”
