Mentor, STMicro collaborate down to 20-nm
With the aim of developing what they are calling "advanced design solutions" at the 32-nm technology node and down to the 20-nm node, the EDA giant and the European semiconductor leader announced a three-year collaboration.
By Ann Steffora Mutschler, Contributing Editor -- EDN, March 19, 2010
With the aim of developing what they are calling “advanced design solutions” at the 32-nm technology node and down to the 20-nm node, EDA giant Mentor Graphics Corp. and European semiconductor leader STMicroelectronics this week announced a broad-scoped, three-year collaboration.
The joint-development project is named DeCADE and was set up to build digital and analog SoC design solutions, including system-level approaches, design methodologies, place and route strategies, optical correction for advanced manufacturing, modeling, electrical characterization and parasitic extraction, the companies explained. ST said it will significantly contribute to the development of these design tools, giving it a head start in its ability to deliver customer-focused semiconductor chips and platforms.
Also, DeCADE is meant to provide design tools for core CMOS technologies and for value-added and application-specific derivative technologies that are developed from the core CMOS process, which are expected to make a fundamental difference in chip capability and performance, as well as in system-solution cost, Mentor and ST said.
The value-added derivative technologies being considered by the DeCADE projects include RF and wireless technologies, 3D packaging and chip stacking technologies.
Geneva-based ST said its participation will assure the strength of the design solutions’ foundation and ensure that its next-generation tools contribute to its maintaining product and technology leadership.
"This joint development effort will provide ST with tools to develop state-of-the-art SoCs at 32-nm and below for ST's customers, taking full advantage of the strong silicon process, device modeling and design know-how present on the Crolles site," said Philippe Magarshack, STMicroelectronics general manager of central CAD and design solutions, in a statement.
"This ST-Mentor Graphics joint effort further reinforces the Crolles cooperative R&D cluster, which already gathers partners that develop and enable low-power SoCs and value-added application-specific technologies and is a great example of a project developed within the framework of the Nano2012 program,” he continued.
Led by ST, Nano2012 is a strategic R&D program that brings together research institutes and industrial partners and is supported by French government. The program aims to create one of the world's most advanced R&D clusters for the development of new generations of semiconductor technology platforms at the nano-electronic level, where the dimensions of the structures used to build the silicon chips are in the order of tens of nanometers, ST reminded.
