P-channel power-MOSFET driver uses unity-gain op amp
Drive a power MOSFET to 100V dc with this signal-conditioning circuit.
Suded Emmanuel, Emmanuel's Controls, Auckland, NZ; Edited by Martin Rowe and Fran Granville -- EDN, January 21, 2010
P-channel MOSFETs can simplify designs when you use them as high-side switches on circuits with voltages exceeding 100V dc. When driving a MOSFET, you must rapidly charge and discharge the input capacitance between its gate and its source to reduce heat losses. The circuit in Figure 1 can accomplish that task. Q7, an International Rectifier IRF5305 power P-channel MOSFET, switches 50V to a load. A series of pulses from a pulse generator or PWM (pulse-with-modulation) source drives the load at frequencies as high as 60 kHz with a variable duty cycle. The circuit comprises Q4, R5, D2, R4, D3, and R3; provides a means of level-shifting; and ensures that the voltage drop between the gate-to-source voltage of Q7 never exceeds 10V. When Q4 is on, 10V develops across D3. This voltage drop turns on Q7 through op amp IC1A, one-half of an MC33072 from On Semiconductor. IC1A has a 13V/µsec slew rate and can drive capacitances as high as 10 nF.
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The combination of D4, R1, Q1, Q2, R2, and C1 provides “ground” for the op amp, which is at 38V—that is, 12V below the 50V rail voltage. The positive voltage is 50V, and ground is 38V. The anode of D3 connects to the noninverting input of IC1A, whose output drives Q7's gate at 40V, which is 10V below the rail voltage of 50V. The circuit comprising R6, Q5, D1, R7, R8, Q6, R9, R10, and Q3 rapidly switches D3's anode to 50V, which turns off Q7. Transistor Q5 functions as an inverter that turns on Q6, which subsequently drives Q3 to rapidly switch D3's anode to 50V and thus drives Q7's gate. Schottky diodes D1 and D2 alternately enhance the switching speed of Q5 and Q4.
Unity-gain op amp IC1A, with its high slew rate, fast settling, capacitive-driving capability, and feedback of the gate voltage, enhances Q7's switching speed. Using this circuit, you can achieve a rise time and fall time of approximately 500 nsec at Q7's output.
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Hi Carl and John, thanks for chiming in. Another concern with the published circuit was brought up by a friend of mine: What would happen if we turned off the supply rather fast? Could it happen that the remaining charge in C1 reversed the supply voltage of the op amp and violated its absolute maximum ratings that likely recommend positive supply voltages only?
For circuits like these, it is always a good idea to use bypass caps right where they are needed: Around 0V for the input circuitry and between 38V and 50V for the high side driver. Using a supply stage like this one, I'd put the cap across Q1.C-E instead of Q2.C-E.
However, I don't want to be disrespectful towards the author who suggested the published circuit. I'd much rather suggest to anyone interested in nice design ideas to keep a box of junk circuit boards around and spend the occasional evening building something cool and simple with just the parts available from these old PCBs. Limiting yourself to parts that are mostly of the standard cheapo kind and still building something interesting is where plenty of nice ideas come from. I am a fan of minimalism and I enjoy concepts like Lars von Trier's "dogma 95" movies, or maybe Henri Cartier-Bresson, who used 50mm lenses only and never modified the frame of the picture after taking it. And let's not forget the cool stuff Dan Flavin created using nothing but plain flourescent lights.
P.S.: I put a typo into my first comment. My suggestion involves three npn BC546B transistors and one pnp BC556B. Two of the npns go into the cascode; a pnp and an npn go into the push-pull-stage between V_B and V_B-12V.
Sebastian - 2010-4-2 13:40:00 PST -
I think Sebastian has the 'good" idea, one that works and is elegant.
John Peterson - 2010-2-2 22:52:00 PST -
Was this a contest to use the most parts in a gate-drive circuit? I got part way through this and my head started hurting. There must be a better way.
Carl Spearow - 2010-2-2 12:08:00 PST -
This certainly is an interesting circuit and I like the trick of using a fast OpAmp as a gate driver near the high supply rail.
However, at least equal performance can be achieved with just four standard small signal transistors (BC546B, BC547B) for a fraction of the cost.
A common emitter npn transistor receives the 5V PWM input and is connected to a common base npn circuit biased at roughly 5...6 V, forming a cascode configuration. The collector resistor of the common base transistor is paralleled with a 1nF capacitor and pulled to +50V via another resistor. The connection of this voltage divider drives a push-pull stage at the gate, forming a high-side PMOS driver. The push-pull-configuration is supplied by a 12V z-diode connected to 0V via 2.2kOhm.
I've tested this circuit successfully up to a few hundred kHz using a 1nF cap as a "dummy" gate of a power PMOS between the output of the push-pull stage and +50V.
Sebastian - 2010-27-1 10:20:00 PST
