Polyphase filters reduce saturation
Polyphase techniques allow you to create large filters in smaller implementations in midrange FPGAs.
By Ron Warner, Lattice Semiconductor Corp. -- EDN, March 18, 2010
| AT A GLANCE |
| In the context of digital signal processing, “aliasing” refers to an effect that causes continuous signals to become indistinguishable from each other.Decimation and interpolation factors can assume only integer values—that is, you can decimate or interpolate only by fractional factors.Digital filters are typically either FIR (finite-impulse-response) or IIR (infinite-impulse-response) types.FIR filters offer several advantages over IIR filters, including the fact that they have completely constant group delay throughout the frequency spectrum and they exhibit complete stability at all frequencies. |
Digital signal processing is ubiquitous in modern electronic systems, from MP3 players to digital cameras to wireless handsets. One of the mainstays of a DSP designer’s tool box is the FIR (finite-impulse-response) filter. The longer the FIR filter—that is, the greater the number of taps—the better the filter’s response. This situation involves a trade-off, however, because more taps require increased logic requirements, increased computational complexity, increased power consumption, and a greater potential for saturation or overflow.
Designers can employ polyphase techniques to implement filters that provide comparable results and use less logic, requiring fewer computational resources, consuming less power, and having less potential for saturation and overflow. The resulting filters fit into today’s new class of smaller, midrange FPGAs.
Some sampling theory
A multirate system uses multiple sampling rates. In some cases—for example, conversion of professional audio into consumer CD-quality audio—a system may sample a signal at one rate, and another portion of the system, operating at a different rate, needs the signal. In this case, you must increase or decrease the sampling rate of the original signal as necessary. Alternatively, the data’s original sample rate may be higher than an application requires. Thus, reducing the sample rate and then operating on the resulting data can dramatically decrease data-throughput requirements, reduce memory requirements, increase processing efficiency, and reduce power consumption.
Let’s first consider the problem of reducing the sample rate. Assume that your system originally sampled a signal at a frequency, F (Figure 1). Now assume that you want to reduce the sample rate to one-fourth of the original frequency. One way of achieving this reduction would be to simply throw away three of every four of the original samples (Figure 2). If you were to discard some samples, the resulting signal could contain aliasing artifacts. In the context of digital signal processing, “aliasing” refers to an effect that causes continuous signals to become indistinguishable from each other after sampling; that is, they become aliases of one another. “Aliasing” also refers to the distortion or artifacts that occur when a signal reconstructed from samples differs from the original continuous signal.
For example, consider an audio signal, such as music, that may contain inaudible high-frequency components. If you sample this signal at too low a rate, which is effectively what you are doing when you discard some samples, and then reconstruct the music with a DAC, you may hear the low-frequency aliases of the undersampled high-frequency components. To avoid this problem, you typically remove the unwanted high frequencies with a lowpass filter before discarding the unwanted samples (Figure 3).
Generally speaking, “downsampling” refers only to the process of discarding samples without performing the filtering operation. By comparison, “decimation” refers to the process of reducing the sample rate—that is, performing the filtering operation and then discarding the samples. In practice, the terms “downsampling,” “downconversion,” and “decimation” are often interchangeable. The “decimation factor,” M, refers to the ratio of the input sampling rate to the output sampling rate. In this example, the input rate is four times the output rate, so M=4.
Consider a situation in which you want to increase the sample rate. The typical reason for doing so is to enable another portion of the system operating at a higher sample rate to work with the signal. Suppose that you start with a signal that the system originally sampled at frequency F (Figure 4). Now assume that you want to increase the sample rate to four times the original frequency. You start by inserting zero-value samples between the original samples to increase the sampling rate (Figure 5). This approach creates a problem, however, because the new zero-value samples add unwanted spectral components to your signal. To solve this problem, you filter the new signal to remove the undesired components and to generate more appropriate sample values (Figure 6).
Technically, “upsampling” refers only to the process of inserting the zero-value samples. By comparison, “interpolation” refers to the process of increasing the sample rate—that is, inserting the zero-value samples and then performing the filtering operation. This DSP form of interpolation differs from the classic mathematical-interpolation methods for constructing new data points from existing data points, but it’s conceptually the same in that it involves generating new values from existing values. In practice, the terms “upsampling,” “upconversion,” and “interpolation” often are interchangeable.
“Interpolation factor,” L, refers to the ratio of the output sampling rate to the input sampling rate. In this example, the output rate is four times the input rate, so L=4 (Figure 7). Note that decimation and interpolation factors can assume only integer values. That is, you can decimate or interpolate only by integer factors, not by fractional factors. In the case of decimation, for example, you can discard only an integer number of samples—that is, one of two, one of three, two of three, three of four, and so forth.
Assume that you want to modify the sample rate of a signal to interface it between two subsystems. If the ratio of the sample rates of the subsystems is an integer value, then you need only perform decimation or interpolation. However, if the ratio of the sample rates is a fractional value, then you must perform resampling, a combination of decimation and interpolation. For example, to resample by a factor of 2.5, you would first interpolate by a factor of five and then decimate by a factor of two to produce an output with a sampling rate of 5/2=2.5 that of the input sampling rate (Figure 8). In practice, this approach combines the interpolation and decimation filters in Figure 8. The term “resampling factor” refers to the ratio between the output sampling rate and the input sampling rate. Regardless of the frequencies involved, you can express this figure as the ratio between the interpolation and decimation factors, L/M, which is 5/2=2.5 in this case.
As another example, consider the process of resampling a professional audio signal captured at a sample rate of 48 kHz for use in consumer audio equipment requiring a sample rate of 44.1 kHz. In this case, the resampling factor equals the ratio of the output rate to the input rate: 44.1 kHz/48 kHz=0.91875 kHz. Looking at this another way, you must change the sampling rate from 48,000 Hz to 44,100 Hz, which means that the output-to-input ratio is 44,100/48,000=441/480=147/160 kHz. Because 147 and 160 have no common factors, you must stop at this point, which means that you must interpolate by a factor of 147 and then decimate by a factor of 160 (Figure 9).
Once again, you can express the resampling factor as the ratio between the interpolation and the decimation factors, L/M, which is 147/160=0.91875. Not surprisingly, this value is exactly the same as the one you obtained from the ratio of the output and input sampling rates because you derived the required interpolation and decimation factors from these rates.
Introducing FIR filters
Digital filters are typically either FIR or IIR (infinite-impulse-response) types. IIR filters use feedback and tend to mimic the response of traditional analog filters. The use of feedback means that their impulse response is recursive and extends over an infinite period of time. Although they require fewer computations than FIR filters, IIR filters may have stability issues, and they cannot match the performance of FIR filters. In comparison, a FIR filter has no feedback, which means that its impulse response lasts for a finite duration of time. FIR filters offer several advantages over IIR filters, including the fact that they have completely constant group delay throughout the frequency spectrum and they exhibit complete stability at all frequencies, regardless of the size of the filter.
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In a generic FIR filter, the input samples, XN, pass through a series of buffer registers, Z–1, corresponding to the Z-transform representation of a delay element (Figure 10). The filter works by multiplying an array of the most recent N data samples by an array of constants, or tap coefficients, and summing the elements of the resulting array. By varying the weights, or values, of the coefficients and the number of filter taps, a FIR filter can realize virtually any desired frequency-response characteristic. The problem is that a FIR filter may require hundreds of taps to achieve its desired goal. Each tap requires a MAC (multiply/accumulate) unit, which consumes logic resources. Also, each tap performs a multiplication operation and an addition operation on every clock, which consumes power.
Performing decimation
The underlying concept of polyphase filters is to split a FIR filter into a number of smaller elements and to then combine the results from these elements. First, consider a symbolic representation of a decimation subsystem using a conventional eight-tap FIR filter (Figure 11). Assume a decimation factor of four and assume that the master clock is running at some frequency, F. As usual, you discard any unwanted samples after the filtering operation has taken place, but this approach is inefficient because it means that you are performing the filtering at the full clock frequency. In other words, every tap stage performs a multiplication and an addition on every clock. In comparison, in a polyphase implementation, you could split your original eight-tap FIR filter into four two-tap subfilters (Figure 12).
Assuming that the same master clock runs at some frequency, F, you can visualize the input data stream as feeding into a rotating switch, which you would implement using standard logic techniques. You feed the first data value to the first subfilter, the second data value to the second subfilter, the third data value to the third subfilter, and the fourth data value to the fourth subfilter. You then loop around so that you feed the fifth data value to the first subfilter, the sixth data value to the second subfilter, and so on.
Using subfilters reduces the potential for saturation and overflow. You typically handle any saturation or overflow that might occur only in the final summing function. In addition, using subfilters provides an immediate efficiency advantage because you are effectively decimating the data before performing the filtering operation. It also means that each of the four subfilters is effectively running at a frequency of F/4 Hz (Figure 13).
In addition to any registers and general-purpose logic, each tap in a conventional eight-tap FIR filter contains a multiplier and an adder, which yields a total of eight multipliers and eight adders. Some additional logic following the filter is also necessary to discard any unwanted samples. Similarly, each tap in the initial four-by-two-tap polyphase implementation contains a multiplier and an adder, which yields a total of eight multipliers and eight adders. The amount of logic necessary for implementing the rotating switch feeding the filters in the polyphase implementation is roughly equivalent to the logic necessary for discarding the unwanted samples in the conventional eight-tap FIR filter. The polyphase implementation also requires some additional logic and an adder to accumulate the results from the four subfilters. Thus, the end result is that this initial polyphase implementation requires a little more logic than does a conventional eight-tap FIR filter.
However, a conventional eight-tap FIR filter must perform eight multiplications and eight additions on every clock. In comparison, the polyphase implementation has only one active subfilter on any main clock. In this example, each subfilter contains two taps, meaning that the filter portion of this function performs only two multiplications and two additions on each clock.
The summing function that gathers the results from the four subfilters also must perform an addition on each main clock. You clear this accumulator to zero at the beginning of each four-clock cycle. The accumulator then gathers the results from the four subfilters and outputs a new value at the end of each four-clock cycle. Each of the subfilters in the initial polyphase implementation is then effectively running at one-fourth the frequency of its counterpart in a conventional eight-tap FIR filter. Thus, the initial polyphase implementation in turn performs only two multiplications and three additions, including the addition that the summer performs, on each master clock, which results in significant power savings. Also, you use each of the four subfilters in this initial polyphase implementation only one-fourth of the time, so you require only one of them at any time, which leads to a slightly more refined implementation (Figure 14).
In this case, you employ a two-tap subfilter, in which each tap contains a multiplier and an adder. On each master clock, you select the appropriate pair of coefficients. Each tap would also require additional registers and logic to maintain context, but this addition is negligible when you consider the reduction in multipliers and adders versus the initial polyphase implementation. You still perform only two multiplications and three additions on each master clock in the polyphase implementation (Table 1).
Performing interpolation
Consider a symbolic representation of an interpolation subsystem employing a conventional eight-tap FIR filter (Figure 15). For the purposes of these examples, assume an interpolation factor, L, of four and a master-clock frequency, F. The upsampling—that is, the process of inserting zero-value samples—takes place before the filtering operation.
Now consider an initial polyphase implementation in which you partition the original eight-tap FIR filter into four two-tap subfilters (Figure 16). In this case, the same input data stream enters all four subfilters, and you generate the main output data stream by alternating between the subfilter outputs. The end result is that this polyphase implementation contains the same number of multipliers and adders as does the conventional eight-tap FIR filter. However, because you filter before you interpolate, the subfilters must run at only one-fourth the master-clock frequency, which results in significant power savings. The master clock samples between the subfilter outputs.
Also, the polyphase implementation requires no upsampling logic, and you could replace the original polyphase-filter implementation with one using a single two-tap subfilter running at the full master-clock frequency and multiplexing the coefficients (Table 2).
In short, you can use polyphase techniques to implement filters that provide comparable results and use less logic, requiring fewer computational resources, consuming less power, and having less potential for saturation and overflow. Polyphase-filter-based decimators, interpolators, and resampling functions are thus ideal for use with smaller midrange FPGAs. Features such as dual-slice architectures and the ability to cascade or chain DSP slices and blocks, available in some new FPGA architectures, make these devices ideal for conventional FIR-and polyphase-based filtering.
| Author Information |
 Ron Warner is marketing manager for SRAM FPGAs at Lattice Semiconductor (Hillsboro, OR). Previously, he was an applications-engineering manager at Agere/Lucent Technologies and a design engineer at Harris Corp. Warner received a bachelor’s degree in electrical engineering from Youngstown State University (Youngstown, OH).
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