EDN’s 20th annual Innovation Awards Finalists
-- EDN, February 18, 2010
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&& PREVIOUS FINALIST | MAIN | NEXT FINALIST >> Category: EDA: Back-End Tools Finalist: In-design DFM with Encounter Digital Implementation System, Cadence Design Systems  At 45 nm and below, systematic variations are the greatest cause of catastrophic chip failures and electrical issues related to timing, signal integrity and leakage power. Ideal-GDSII shapes (squares or rectangles) get converted into contours on silicon, irrespective of any post-tapeout manipulation of GDSII data. This results in variability leading to catastrophic and parametric failures. Several EDA vendors have design-side litho hotspot analysis tools. Cadence’s tool, Litho Physical Analyzer uses physical models, calibrated with foundry data, and is used widely for litho hotspot analysis. However at 32nm and beyond, the widening lithography/manufacturing gap leads to a dramatic increase in design rules. The sequential communication between the router and the signoff litho analysis tools becomes a bottleneck at advanced nodes. In 2009, Cadence introduced in-design DFM with Encounter Digital Implementation System, which is over 100x faster than signoff litho analysis. Unlike the signoff litho analysis, EDI System has built-in litho pattern knowledge and aggressive filtering, screens the design during routing for potential areas which could fail on silicon, and automatically eliminates hot spots. This approach is the first in the EDA industry and approaches model-based litho closure during routing. EDI System does not guarantee a full litho hotspot closure but eliminates the vast majority such that it drastically reduces the signoff litho runtime. |
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