Circuit lets you test sample-and-hold amplifiers

Measure voltage drop with a digital voltmeter.

Marián Štofka, Slovak University of Technology, Bratislava, Slovakia; Edited by Martin Rowe and Fran Granville -- EDN, March 4, 2010

Sample-and-hold amplifiers sample an analog voltage and hold it until an ADC can digitize it. A perfect sampling circuit holds a voltage until digitizing is complete. Thus, the amplifier’s output is identical to its input. Real sample-and-hold amplifiers, however, can gain or lose voltage, producing an error. Offset voltages in amplifiers cause a static additive error. Further, there occurs a specific additive error, the so-called voltage pedestal, which originates within the transition from the sample state to the hold state because of a parasitic charge transfer to the hold capacitor.

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A sample-and-hold amplifier uses an analog switch to connect a signal to a holding capacitor. When the switch closes, thus having low resistance, the capacitor charges to the sampled input voltage. During the hold time, when the switch has high resistance, the sampling capacitor holds the voltage until the ADC digitizes it. During the transition from low to high switch resistance, a parasitic charge injection, mainly from the gate of the switch to the hold capacitor, continues to charge the capacitor until the switch’s control voltage reaches a steady logic level. The injected charge produces an error voltage at the capacitor. Additional errors may occur during the hold time. Leakage and bias currents in the amplifier combine with tens of picoamps of leakage current in the switch and capacitor to cause the capacitor to charge or discharge during hold time.

By applying a logic-control signal with a duty cycle of D and 1–D, you can measure a mean output voltage difference, [ΔV_OUT]=[V_OUT–V_IN], which the following equations show. [ΔV_OUT]=V_STAT+ (1–D)V_INJ+½(1–D)²V_DROPPEAK, and [Δ]=V_STAT+DV_INJ+½D²V_DROPPEAK, where ΔV_OUT and 
Multiplying the voltage pedestal, a simple rectangular waveform, by the duty cycle yields the average value. In contrast, the voltage-drop waveform appears as a sawtooth. Its mean rises as one-half of the duty cycle squared. The peak-voltage-drop value denotes a hypothetical voltage drop at the end of a whole period, T, of the SAMPLE/ logic-control waveform.

You can use the previous equations to find the values of the voltage pedestal and the peak voltage drop. A 75% duty cycle is a convenient value. The following equations are valid for this duty cycle: V_INJ=6[ΔV_OUT]–2/3[Δ]–16/3V_STAT, and V_DROPPEAK=16[–[ΔV_OUT]+1/3[Δ]+2/3V_STAT]. You must find the optimal repetition rate, f_REP, of the logic-control signal. As the optimal repetition rate increases, the difference in output voltage from the input is almost purely due to dc voltage offset plus the voltage pedestal: (–V_STAT)/(V_OUT–V_STAT)≈3. The following equation finds the maximum value for the optimal repetition rate: f_REP≤(0.01/4)×1/(t_ON–t_OFF), where t_ON and t_OFF are the on and off times, respectively. This equation ensures that the difference in values between the turn-on and turn-off times of the sample-and-hold amplifier’s internal analog switch won’t affect the accuracy of the precision 25 and 75% duty cycles by more than 1%.

If you evaluate the equation for a high-performance analog switch, such as the Analog Devices ADG1213, you get a repetition rate of 33 kHz or less. The difference due to voltage drop prevails at low-value repetition rates. In this case, the repetition rate can be the value of the frequency at which –V_STAT≤1/10×V_INMAX, where V_INMAX is the maximum input-voltage range. The best way to determine the lower limit of the repetition rate is through experimentation.

Reference

“Low Capacitance, Low Charge Injection, ±15 V/+12 V iCMOSTM Quad SPST Switches,” Analog Devices Inc, 2005.