EDN’s 20th annual Innovation Awards Finalists
-- EDN, February 18, 2010
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&& PREVIOUS FINALIST | MAIN | NEXT FINALIST >> Category: EDA: Front-End Simulation and Database Tools Finalist: Virtuoso Accelerated Parallel Simulator, Cadence Design Systems  Advanced process technologies and modern integrated circuit (IC) designs with complex design metrics and stringent standards have turned analog and RF simulations into multi-day to multi-week engineering tasks. As a result, we need a holistic and optimized simulation solution that incorporates analog, RF, and AMS, especially at or below 90nm. The Cadence® Virtuoso® Accelerated Parallel Simulator addresses the challenges of accuracy degradation of results, excessive run times and huge learning curves for setup and post-processing. Accelerated Parallel Simulator delivers the full accuracy of the industry reference Cadence Virtuoso Spectre Circuit Simulator. It improves convergence and capacity for designs with hundreds of thousands of transistors and parasitic elements, including Phase Locked Loops, Data Converters, Memory IPs, power-management circuits and full-chip designs. Accelerated Parallel Simulator combines proven Cadence simulation technologies, a breakthrough advanced parallel circuit solver, and a newly-architected multiprocessing engine that runs on multi-core compute platforms up to 16 cores. APS also addresses performance and capacity challenges. The result is a next-generation performance circuit simulator with full SPICE accuracy; significant performance gain single-thread and multi-thread; improved DC, transient and RF analysis convergence; and a much larger capacity foot print. |
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