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EDN’s 20th annual Innovation Awards Finalists

-- EDN, February 18, 2010



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Category: Innovator of the Year
Finalist: Xilinx Spartan-6/Virtex-6 FPGA design team




For most design teams, bringing a single IC to market on the latest silicon process is a monumental achievement. In 2009, amid the worst economic downturn in modern history, Xilinx engineers took this challenge to the next level, simultaneously rolling out two flagship FPGA families—Virtex-6 and Spartan-6—on the latest 40- and 45-nm process technologies with longtime foundry partner UMC and new foundry partner Samsung.

What’s more, the Spartan-6/Virtex-6 FPGA Design Team executed in under 24 months, setting new industry benchmarks for performance, power, price, and densities to meet a diverse set of system-level requirements across multiple markets and exploiting the benefits of Moore’s Law with up to 12 layers of metal interconnect and 2.5 billion transistors.

To pull off such an epic feat required precise planning and rigid execution by a multinational, multidisciplinary engineering team focused on managing design complexity by taking a unified approach to all aspects of IC design, beginning with a common fabric architecture for both device families.

Product definition kicked off in 2007 by interviewing hundreds of system designers. Over a two-year period, Steve Douglass, Suresh Menon, and Dan Lenehan led a global 250-member silicon design team organized into 10 "Centers of Excellence," each with hardware and software designers focused on a specific block or subsystem. Moreover, they managed three distinct design flows while addressing the infrastructure challenges associated with 40/45-nm development. And they instituted a new cross-functional "Technical Solutions Team" to enable trade-off decisions across device families.

The design team’s efforts paid off. Through a combination of advanced silicon technology, innovative circuit design techniques, and architectural enhancements, next-generation Virtex-6 and Spartan-6 FPGAs offer up to 25% higher performance, 65% lower power consumption, and 60% higher logic density, compared with previous generations, and achieve over 1-Tbps bandwidth. And both families offer low-power device options for power-sensitive applications.

EDN INNOVATION AWARDS





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