EDN’s 20th annual Innovation Awards Finalists
-- EDN, February 18, 2010
|
&& PREVIOUS FINALIST | MAIN | NEXT FINALIST >> Category: EDA: Front-End Analysis and Synthesis Tools Finalist: IC Validator in-design physical-verification solution, Synopsys  IC Validator, Synopsys’ new In-Design Physical Verification solution, unites the worlds of physical design and verification. Working in concert with IC Compiler, IC Validator allows physical designers to efficiently conduct signoff-quality verification during the design process. Errors are automatically detected and fixable in the full context of area, timing, and power, before the design is closed. The end result is a DRC-clean design that passes the final signoff with ease. IC Validator is integrated with and built on the shared data model with IC Compiler. The signoff-quality accuracy is proven through extensive foundry qualification. The modern implementation uses hybrid polygon/edge rule processing, is multicore enabled, and employs a unique programmable language for concise rule creation and execution. Early users are reporting 10X smaller rule decks, 7X speedup on 8 cores, and 10 to 20X faster metal fill. |
|
Talkback
