EDN’s 20th annual Innovation Awards Finalists
-- EDN, February 18, 2010
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&& PREVIOUS FINALIST | MAIN | NEXT FINALIST >> Category: EDA: Front-End Analysis and Synthesis Tools Finalist: RootCause analyzer formal diagnosis tool, OneSpin Solutions  OneSpin’s new RootCauseAnalyzer reduces debug time and effort in formal assertion-based verification (ABV) by up to 10X. It automates the analysis and debug of SystemVerilog Assertions (SVA) and RTL code, eliminating most of the manual effort required by traditional debug approaches – effort that constitutes up to 40 percent of the total verification effort. The primary innovation of the RootCauseAnalyzer is a patented SVA source code debugger that automatically identifies the failing part of assertions of any degree of complexity. The debugger reads the values of signals from the counterexample and performs a semantic analysis that annotates all objects at all clock cycles in the assertion (signals, local variables, functional calls, parameters, etc.) with values according to the counterexample. A second semantic analysis explores the logical/temporal structure of the assertion and evaluates all Boolean expressions at all clock cycles to find the time point(s) and the sub-expression(s) that make the assertion fail. Violated sub-expressions are marked in red at the respective clock cycles. Additionally the source code debugger analyzes the hierarchical structure of the SVA (nested function calls, instantiations of named sequences and properties) and generates a hierarchical view of the assertion that can be interactively explored by the user – using unfolding and/or collapsing parts of the SVA. In addition, the RootCauseAnalyzer features advanced waveform analysis, automatic tracing of signal dependencies across clock cycles and module boundaries, and automatic identification of those RTL code regions that are involved in the assertion failure. |
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