EDN’s 20th annual Innovation Awards Finalists
-- EDN, February 18, 2010
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&& PREVIOUS FINALIST | MAIN | NEXT FINALIST >> Category: Network, timing, and BER test Finalist: J-BERT N4903B jitter-tolerance tester, Agilent Technologies  Data rates of serial interconnects inside computers and communication devices continue to increase to handle video, mobile, and Internet applications. Data rates of 5 Gbps and beyond cause significant signal-integrity issues for chip, modules, and PC-board designers. Emerging technologies can help to overcome challenges, but they require adequate and accurate testing. Agilent’s new J-BERT N4903B offers complete jitter tolerance test for characterizing emerging serial bus interfaces, supporting both embedded and forwarded-clock devices up to 14.2 Gbps data rates. It allows accurate and efficient characterization of forwarded-clock devices, such as QPI, HyperTransport, or memory buses. J-BERT also allows accurate receiver characterization with its unique capabilities, such as variable duty cycle distortion on half-rate clocks, delayable jitter on clock and data signals, variable de-emphasis, and the new clock doubler accessory. Agilent says customers using J-BERT N4903B claim significant efficiency gain because it reduces the test setup and complexity considerably. Key contributions are the integrated and calibrated jitter sources that allow generation of stress conditions for multiple serial bus interfaces; variable output levels and rates on data and clock signals; powerful pattern sequencer for simplified setup of training sequences; automated jitter tolerance test routines; and fast total jitter and eye measurement routines. Agilent also offers an upgrade path from the N4903A. |
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