Making Gaussian edges
When simulating high-speed systems in Spice, you can use an analog-filter network instead of PWL (piecewise-linear) edge-shaping because it better represents how real signals behave.
By Howard Johnson, PhD -- EDN, December 3, 2009
The analog-filter network in Figure 1 converts each input step into a smooth, Gaussian-shaped rising and falling edge. When simulating high-speed systems in Spice, you can use this filter network instead of PWL (piecewise-linear) edge-shaping because it better represents how real signals behave.
The analog filter comes from Anatol I Zverev’s Handbook of Filter Synthesis, a classic compendium of passive-filter designs (Reference 1). The book lists circuits for implementing many types of filters, including approximations of the Gaussian filter. The approximation is not exact because an actual, perfect, Gaussian response would have an infinitely long precursor. The author derives the filter approximation as a 10th-order truncation of the Taylor series expansion for the square of a perfect Gaussian-network function. He assumes ideal components with no significant parasitic effects.
Zverev specifies a current-source driver for the filter and shunts the current source with resistor R0. Figure 1 drives the circuit differently. It uses a voltage source that connects in series with R0. Either approach produces a driver with an output impedance of 50Ω. Using a voltage source ensures that the circuit’s output amplitude will be precisely half the voltage source’s amplitude.
The circuit values in black in Figure 1 differ from the original circuit values in Zverev’s book, which the figure shows in red. The author designed his circuit for an impedance level of 1Ω. Figure 1 scales that impedance to a more commonly accepted value of 50Ω. It does so by multiplying the book’s resistances and inductances by 50 and dividing the capacitances by 50.
The 3-dB frequency of Zverev’s original circuit equals 1 rad/sec, or 0.159154 Hz, making a 10 to 90% rise/fall time of 2.12773 seconds. Figure 1 scales the filter to a 100-psec rise time by multiplying all the capacitor and inductor values by the ratio τ/(2.12773), where τ is the desired rise time. This time-scaling operation leaves the resistor values unchanged.
The combination of impedance- and time-scaling operations in Figure 1 produces a 50Ω filter with a 100-psec rise and fall time. The filter tracks true Gaussian behavior down to –40 dB within ±1 dB, with a slope of 60 dB per octave after that (Figure 2). The nominal delay of the 10-pole model, from zero to 50%, is 1.485 times the 10 to 90% rise time. Remember this delay when making your timing calculations. You’ll see it in the Spice model.
Always follow Zverev’s filter with a buffer. In Spice terminology, a perfect buffer is a VCVS (voltage-controlled voltage source). The buffer prevents any attached loads from changing the filter’s performance. Connect your driver’s source-resistance and package models to the output of the buffer.
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