Transistor junction leakage current drops by 10x in research report
A single process change could produce transistors much better suited to low-power designs.
By Ron Wilson, Executive Editor -- EDN, December 4, 2009
Research to be reported jointly by IMEC and Applied Materials at the International Electron Devices Meeting next week has indicated that a seemingly minor improvement in the front-end-of-line process for advanced CMOS ICs can have a significant impact on junction leakage, one of the components of standby power consumption in low-power chip designs. The companies will report a reduction of up to an order of magnitude in leakage current, with immediate implications for designers of low-power ICs.
The single processing stage in question is the annealing of nickel silicide to prepare the contact area for the transistor source and drain regions. The silicide is necessary to form a low-resistance connection between the source and drain material and the contact plugs that connect the source and drain to the copper interconnect stack. At first glance contact formation would appear to be unrelated to leakage resistance, but research into the details of the way nickel diffuses into silicon has, to the apparent surprise of the researchers, shown otherwise. Applied Materials product manager Swami Srinivasan explained that there are several steps necessary to form the silicide in today's recessed-source/drain, ultra-shallow-junction MOSFETs. In brief, after depositing the spacer around the gate stack and growing epi on the source and drain, you deposit a layer of metallic nickel over the wafer. Then you do a moderate-temperature, relatively slow anneal to drive nickel atoms into the epitaxial silicon. You then strip the remaining nickel from the surface of the wafer, and finally you do a second, higher-temperature anneal. This last step needs to get the source/drain regions hot enough to change the phase of the silicide from Ni2Si to lower-resistance NiSi, without putting so much energy into the area that it causes substantial further diffusion of the Ni. The result is a thin, low-resistance contact region on the surface of the source and drain, ready to receive the contact plug. That requirement for high temperature over a short time has induced equipment manufacturers to turn to laser-powered millisecond-anneal systems for this second anneal step. And introduction of millisecond anneal is in turn the key to the leakage reduction, Srinivasan explained. The explanation lies in the behavior of the Ni atoms once they are diffused into the source and drain regions after the first, slower anneal cycle. Research has discovered, Srinivasan said, that nickel has a particular affinity for discontinuities—and especially defects—in the silicon lattice. "It decorates them very quickly," he stated. Unfortunately for the transistor, it appears from research so far that the nickel atoms have a particular fondness for two particular features: the interface at the outside ends of the transistor where the source and drain diffusions meet the isolation trenches and long, narrow voids that run along an axis of the silicon lattice from the source and drain regions toward, or into, the channel. By migrating into these areas, the nickel forms, respectively, a low-resistance path from the source or drain into the substrate, and a narrow sliver of low-resistance metal—called piping—up to or even through the junction and into the channel region. Both of these low-resistance paths enhance leakage. And using millisecond anneal for the phase-changing annealing step appears to sharply reduce the formation of both types of paths. It is the extent of reduction that surprised researchers. UMC had previously demonstrated an improvement of 3 to 4% in total Ion/Ioff using the technique, based mostly on the reduction in piping defects. But the IMEC paper will report the possibility of an order of magnitude improvement in junction leakage under slightly different processing conditions, apparently based both on reduced piping and on reduction in nickel migration along the transistor/trench interface. Given that high-k/metal-gate processes have already reduced what had been the largest component of transistor leakage—sub-threshold current from source to drain—these improvements in other leakage currents now directly improve circuit performance of the transistors. "The take-away message here is that the improvement in leakage current from using millisecond anneal can be very substantial, but it depends a great deal on the structure of the device and on process integration," Srinivasan said. Another observation is that at advanced geometries, we are forming the whole planar transistor in what used to be the surface region of the transistors at larger geometries. Tiny areas of silicon—such as the source/drain extensions under the gate stack, the wall where the ends of the source and drain meet the isolation trenches, and the edges of the silicide diffusion—can have a disproportionate impact on the performance, and the reliability, of the transistor. Expect more surprises, both pleasant and not so pleasant, as researchers explore further into the nature of the smallest possible planar transistors.
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high-k should directly address gate leakage, the subthreshold leakage not so obvious.
yt - 2009-6-12 18:26:00 PST -
Note: the leakage reduction of 10x in this story refers to junction leakage, not total Ioff current. There are other, larger components to total leakage current.
ron
Ron Wilson - 2009-4-12 20:33:00 PST
