Emulate SPI signals with a digital-I/O card
Four I/O lines let you test microcontroller-based products.
Andy Street, Autoliv Electronics, Lowell, MA; Edited by Martin Rowe and Fran Granville -- EDN, September 17, 2009
A design-verification tester for millimeter-wave SOC (system-on-chip) devices needed to combine switching, electrical measurements, temperature measurement, a parallel-digital interface, and a serial-digital interface into one instrument. To minimize rack space, the circuit uses an Agilent Technologies 34980A multifunction mainframe because its plug-in cards could support a force/sense dc matrix and multiplexed temperature measurements. The addition of an Agilent 34950A 64-bit digital-I/O card formed the basis of a system that could provide both an SPI (serial-peripheral-interface) bus and a simple parallel bus. The 34950A groups its I/O lines into two banks of four 8-bit channels. It provides 64 kbytes of memory per bank for pattern generation or signal capture. It also has three I/O lines per bank for handshaking. However, the card's handshake lines provide insufficient control for implementing SPI transactions. To get adequate control, you can emulate the SPI bus using three of the data-I/O lines.
Motorola microcontrollers first used the SPI master-slave protocol. Today, it's become the control interface in a variety of ICs, including PLLs (phase-locked loops) and RF ASICs (reference 1 and reference2). The SPI bus uses the clock, SS (slave-select), MOSI (master-out/slave-in), and MISO (master-in/slave-out) lines. The clock line is a signal from the master to the slave. All SPI signals are synchronous with this clock. The SS line selects the slave for communication. The SPI specification defines four modes of operation, which effectively specify the clock edges for toggling and sampling and the clock-idle level. The specification makes no requirements on voltage levels or data rates, and many SPI implementations can clock in excess of 10 MHz. Figure 1 shows a block and timing diagram of the 34950A's Bank 1, configured for synchronous, buffered output. H0 through H2 denote the handshake lines. The figure also shows an 8-bit SPI transaction for reference.
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You cannot use the 34950A's handshake lines to emulate all modes of the SPI bus because the bus latches data on the falling edge of the clock, making the bus unsuitable for slaves that use the rising edge. Inverting the clock polarity is not a solution because you may lose the last data bit. Furthermore, if you write a number of transactions to a slave, you must store each transaction as a separate trace memory in the 34950A. Although each bank supports 64k×8 bits, you can store a maximum of 32 traces in the pattern RAM per bank, thereby limiting the number of SPI transactions. In addition, the card lacks a sequencer, so you cannot download a number of bit patterns and then play them in sequence. You must load each pattern into the I/O card's memory and then play each pattern under SCPI (standard commands for programmable instruments) from a host computer, slowing transactions.
Instead of using the handshake lines, this solution uses three data-I/O lines to emulate the SPI clock, SS, and MOSI. The software driver for the I/O cards then has the responsibility of translating the data to be sent into an SPI-compatible bit stream. Listing 1 contains the algorithm in pseudocode, which translates a hexadecimal string, DH, of characters to an SPI signal. LD, LSS, and LCLK are integers to define which data outputs represent the MOSI, CLK, and SS, respectively.
Assuming a 24-bit register write with two bits of overhead for the SS prefix and postfix, the 64-kbyte memory can support more than 1000 SPI transactions. The approach has two additional advantages: The three lines that form the SPI bus are under software control, which provides cabling flexibility, and the implementation can support multiple slaves through the use of additional SS lines. Figure 2 shows an MSO (mixed-signal-oscilloscope) screen that shows the SPI transaction. The SPI clock rate is 5 MHz, which the 34950A's internal 10-MHz clock limits. The different payload sizes correspond to writing data to 16- and 24-bit registers within the slave.
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