Openness and cooperation create healthy EDA ecosystem
GUEST OPINION: Competition brings progress, but it helps the customer only if we respect standards and the need for interoperability.
By Nimish Modi, Cadence Design Systems -- EDN, September 29, 2009
There's no doubt that the EDA industry has become increasingly competitive as total industry revenues have experienced a recent downturn and major customers have grown cautious with their spending. In spite of the stepped-up competition, we at Cadence believe strongly that openness and cooperation are in the best interests of all stakeholders—including EDA vendors, partners, and customers. Specifically, Cadence has reaffirmed its commitment to industry standards by actively participating in nearly every ongoing EDA industry standard effort, and has also returned to an active role in DAC (Design Automation Conference).
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Cadence has taken a strong role in driving and supporting industry standards for many years. The commitment to standards dates back to the early days of Cadence, when Verilog was offered as an industry standard. More recent initiatives include the donation of the OpenAccess database through the Si2 (Silicon Integration Initiative); the creation, along with Mentor Graphics, of the open-source OVM (Open Verification Methodology); and the development of a TLM (transaction-level modeling)-based design and verification flow based on OSCI (Open SystemC Initiative) TLM standards.
OVM is an excellent example of what can happen when two head-on EDA competitors come together to solve an industry problem. Several years ago, the three major EDA vendors—Cadence, Synopsys, and Mentor—were pursuing their own verification methodologies, and customers were concerned because none of these methodologies ran on more than one simulator. Cadence and Mentor Graphics agreed to jointly develop a common verification methodology that would run on both companies' platforms. Today, more than 55 companies partner to provide support for OVM. Cadence and Mentor, meanwhile, have chosen to differentiate themselves not by locking customers into a proprietary methodology, but through technology offered on top of a common open-source methodology.
The full extent of Cadence's involvements in formal industry standards efforts is not widely known. Cadence today holds officer positions and board positions in the Accellera, SPIRIT, and OSCI standards organizations, and Cadence engineers are active in every working group and technical subcommittee of each of these organizations. Indeed, current Cadence employees played key leadership roles in the formation and ongoing operation of all three of these organizations. Furthermore, as an IEEE Standards Association corporate member, Cadence votes on every IEEE EDA standard. Cadence is also active in every working group of the IEEE DASC (Design Automation Standards Committee) and holds an officer-level position in the DASC.
To support low-power IC design, Cadence originated the CPF (Common Power Format), which has seen strong customer adoption and third-party support. Even so, Cadence today is firmly committed to enabling interoperable low-power flows regardless of the customer's choice of power formats. CPF is currently managed by the Si2's user-driven LPC (Low Power Coalition), which, as described in a recent DAC workshop, is also working toward driving interoperability between CPF and IEEE P1801 (Unified Power Format).
Today, there's a strong push toward design at higher levels of abstraction, using ESL (electronic system level) design and verification technologies such as high-level synthesis and virtual platforms. Cadence is actively involved in that movement and is basing its strategy on industry standards, including the OSCI TLM 2.0 model interoperability standard. Many early attempts at ESL failed, largely because of a lack of standards. It is now clear that ESL cannot succeed without strong standards support.
The donation of the OpenAccess database helped spark some competition for Cadence's analog and custom IC design solutions. Even though it's a considerable investment, Cadence continues to provide reference implementations for OpenAccess. Meanwhile, on July 23 Cadence announced an ongoing collaboration with TSMC to support and enhance TSMC's recently announced iPDKs (interoperable PDKs) in the Cadence environment.
It takes a lot of resources to develop and deploy standards, and standards can create new openings for competitors. So why support standards and interoperability? One reason is that customers are increasingly demanding it. Customers want flexibility and choice; they don't want to be locked into single-vendor design environments by proprietary formats or methodologies. They want vendors to add value on top of standards-based platforms by providing the best available technology, solutions, and services.
Even with interoperability, however, there is still a need for cohesive design systems. The complexity of design and verification problems has risen to a point where we cannot solve them in isolation by simply applying better point tools. We need to take a flow-driven approach toward solving tough problems, creating integrated solutions for challenges such as enterprise verification, mixed-signal design, and low power. Flexibility is highly desirable, but at the end of the day, what's most important is having an optimized solution that can solve the customer's problem.
Another aspect of Cadence's renewed drive to fully participate in the EDA ecosystem is our re-entry into DAC. In addition to exhibiting in several booths, Cadence sponsored this year's User Track and Management Day sessions and offered user presentations and panels in our Ecosystem booth. Cadence is also now active in the EDA Consortium, where Lip-Bu Tan, Cadence president and CEO, serves on the board of directors.
Customers are pushing for standards and interoperability more loudly than ever. No one really wins when customers are locked into proprietary systems, and everyone wins when customers have flexibility and choice. As vendors differentiate themselves by offering better solutions rather than creating proprietary barriers, we will be much better equipped to handle the challenges of IC and systems design over the next decade.
Looking forward, openness and EDA industry cooperation will become even more important. With increasing design complexity, and shrinking times to market, the design and verification problems facing us are too big to be solved by any one vendor alone.
| Author Information |
 Nimish Modi is senior vice president of research and development for the Front-End Group at Cadence Design Systems. In this role he has responsibility for products and solutions in the areas of logic design, systems design, verification, SoC IP integration, and hardware/software co-validation. Prior to joining Cadence in 2006, Modi spent 18 years at Intel Corp, where he was most recently a vice president in the Enterprise Platforms Group with responsibility for the company's server CPU development, including the Xeon and Itanium product families. He also held various senior R&D and leadership positions as a member of i486, Pentium, and Pentium II processor teams and led the development of Intel's first optimized Celeron processor. Modi holds a bachelor's degree in electrical engineering from the University of Bombay and a master's degree in electrical engineering from Virginia Tech.
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