Secondary-side synchronous rectification boosts resonant converter efficiency
While secondary-side synchronous rectification in resonant half-bridge topology is not uncommon, its implementation has not been easy. A novel control scheme precisely turns on and off the secondary-side synchronous rectifier MOSFETs to achieve rectification that emulates a Schottky-diode rectifier, minimizing switching losses and optimizing conversion efficiency.
By Helen Ding, International Rectifier -- EDN, November 19, 2009
When it comes to efficiency, every bit helps. Designers now are borrowing ideas from higher-power (200W and above) designs to squeeze every watt from low-power designs—50 to 200W. Consequently, the recent trend for 50 to 200W dc/dc converters, employed in flat-screen TVs, game consoles, laptop adapters, and other home-entertainment applications, has been to exploit the use of SSSR (secondary-side synchronous rectification) in resonant half-bridge topology for higher conversion efficiency, lower EMI, and better power density.
But, in practice, implementing SSSR in a resonant topology has been challenging. As resonant tank input and output voltages are not in-phase, it is not easy to synchronize signals from the primary to drive the secondary MOSFETs. Consequently, a novel control scheme has been developed that operates independent of the primary-side switching and does not require any synchronization. By accurately sensing the voltage across the secondary MOSFETs, the new control technique precisely turns on and off the synchronous rectifier MOSFETs. This approach emulates a Schottky-diode rectifier with the benefits of a MOSFET device. Since MOSFET conduction loss is the product of drain current and drain-source on-resistance RDS(on), keeping RDS(on) very low translates into significant reduction in power dissipation in the device. The result is minimum power loss and maximum conversion efficiency.
SR control scheme
Fundamentally, this unique control scheme senses the voltage across the MOSFETs and compares it with two negative thresholds to precisely determine the turn-on and -off transition for the devices. A higher negative threshold, VTH2, detects current through the body diode and hence controls the turn-on transition for the power device. Similarly, a second negative threshold, VTH1, determines the level of the current at which the device turns off as shown in Figure 1. Control logic incorporated in the new scheme minimizes parasitic effects and prevents false turn-on and -off as well as gate chattering when the device current transitions between its body diode and the channel. Also, the control circuit is designed to handle wide VCC operating supply, allowing it to be directly powered from the converter output.
The turn-on and turn-off propagation delays are very low, as shown in Figure 2, to provide turn-on and turn-off in close proximity of zero-current transition. It is estimated that for a typical rise time tr of 10 ns and a fall time tf of 5 ns, the propagation delays tDon and tDoff are typically 60 and 70 ns, respectively.
Two high-voltage, high-speed comparators sense the drain to source voltage (VDS) of the MOSFETs differentially, while the device current is sensed using the RDS(on) as a shunt resistance and drives the gate pin of the MOSFET accordingly. Dedicated internal logic turns the power devices on and off at the zero-current transition (Figure 3).
Turn-on and turn-off
When the conduction phase of the SR (synchronous rectifying) MOSFET is initiated, current will start flowing through the MOSFET body diode, generating a negative VDS voltage across it. The body diode has generally a much higher voltage drop (0.5 ~ 0.7V) than the one caused by the MOSFET on-resistance. The body diode voltage drop will trigger the turn-on threshold, VTH2. The VTH2 threshold is kept small enough to shorten the body diode conduction time and large enough to offer noise immunity. Hence, a reasonable range is −100 to −300 mV. And −140 mV was selected.
When VTH2 is triggered, the control circuit will drive the gate of the MOSFET on. This will in turn cause the VDS to drop down to ID×RDS(on). This drop is usually accompanied by some amount of ringing that could trigger the input comparator to turn off; hence, a fixed MOT (minimum on-time) blanking period is used that will maintain the power MOSFET on for a minimum time duration. Typically, the MOT is set to 750 ns. The fixed MOT limits the minimum conduction time of the secondary rectifiers and, hence, the maximum switching frequency of the converter.
Once the MOSFET has been turned on, it remains on until the rectifier current decays to the level where VDS will cross the fixed turn-off threshold VTH1. Since the device currents are sinusoidal here, the device VDS will cross the VTH1 threshold with a relatively low di/dt. Once the threshold is crossed, and the gate is turned off, the current will start flowing again through the body diode, causing the VDS voltage to go negative. Depending on the amount of residual current, VDS may once again trigger the turn-on threshold. To prevent false turn-on, VTH2 is blanked for a set time duration tBLANK after VTH1 is triggered, as shown in Figure 4. When the device VDS crosses the positive reset threshold VTH3, tBLANK is terminated and the control circuit is ready for next conduction cycle, as shown in Figure 4. Typically, the blanking pulse duration tBLANK is about 17 μs.
To maximize channel conduction time and minimize body diode conduction time, turn-off threshold VTH1 is chosen closer to zero as possible. Hence, it was selected to be −6 mV.
Smart rectifier chip
The control circuit described above and depicted in Figure 3 has been incorporated on a single chip using Gen 5 HVIC process technology. With two on-chip gate drivers, this smart secondary-side control chip, IR1168, is capable of driving two N-channel power MOSFETs used as synchronous rectifiers in isolated dc/dc resonant converters. Fundamentally, it senses the drain-source voltage across the MOSFETs using the two high-voltage (200V), high-speed comparators. The internal dedicated logic ensures that the MOSFETs turn on and turn off in close proximity to the zero-current transition. By preventing spurious gate transitions and false turn-off, the internal blanking scheme of the chip, represented in Figure 4, guarantees operation in both fixed and variable frequency modes. A typical LLC resonant half-bridge implementation using the control chip IR1168 and the two MOSFETs (SR1 and SR2) is illustrated in Figure 5. As seen in the system-level circuit in Figure 5, only three external passive components are needed besides the MOSFETs to complete this design: two SR MOSFET gate resistors Rg1 and Rg2 and the supply decoupling capacitor Cdc.
Since the SR MOSFETs turn on and off at VDS levels close to zero, the gate resistors Rg1 and Rg2 do not have any impact on these transitions. Therefore, to avoid loop oscillation it is calculated using the relationship in equation 1.
where Lg is the total gate trace loop inductance and Ciss is the MOSFET input capacitance.
Additionally, the gate resistors also share the gate driver power losses with the control chip IR1168. Per the well-known series RC network transient, the energy dissipated by the resistor is exactly equal to the energy stored in the capacitor. Here the capacitor refers to the equivalent gate charge capacitor of the synchronous MOSFET. The IR1168 internal gate driver is of course always in series with the external gate resistor, which means they will linearly share the power dissipation.
Using Equation 2, Vcc is calculated for a variety of converter switching frequencies and different synchronous MOSFET gate capacitance Csync with two different values of total gate resistance Rg1,2. The results are plotted in figures 6 and 7.The Vcc calculations for figures 6 and 7 assumes that TJ(max)=125°C, the control IC ambient temperature is 55°C, and the sync FET internal gate resistance is 1§Ù. In fact, the total gate resistance Rg1,2 includes both internal and external gate resistances:
where
PRg1,2 is the total driving power dissipated in the gate resistors Rg1,2, and ICC is the operating current of the control chip IR1168. Vghigh is the IR1168 gate driver output voltage, while fSWmax is the maximum converter switching frequency.
Figures 6 and 7 clearly indicate the relationship between these parameters and how the supply voltage and gate resistor play a major role in the design trade-off. The quick charts enable the designer to pick an optimum combination of switching frequency, supply voltage, and gate resistance.
In the case the chip is powered directly from the output, the minimum decoupling capacitor value is calculated as per Equation 3:
RCC
is the series current limit resistor on the supply side. The calculated value may vary with different systems. A minimum 1-μF ceramic capacitor is recommended for noise decoupling.
Since MOSFET package inductance can result in a voltage drop under transient current di/dt, that can offset the on/off threshold levels to degrade the effectiveness of the voltage-sensing control technique. It is critical to keep this stray inductance to a minimum. Surface-mount packaged synchronous MOSFET is preferred than through-hole package. The DirectFET is a good match device for synchronous rectifier application.
Working design example
To demonstrate the benefits of the novel control technique proposed here, a 24V-dc rail in a 240W LCD TV ac/dc SMPS (switch-mode power supply) was retrofitted with SR MOSFETs IRF7854PBF using the new control chip IR1168, as shown in Figure 8. In fact, in this retrofit design example, the two SR MOSFETs in SO8 packages replaced Schottky diodes in the original solution.
The efficiency and thermal performance for the retrofit ac/dc board was measured for both 160 and 240V-ac inputs with converter switching frequency fSW of 100 kHz. The rectified output was 24V dc at 7.5A continuous current.
There was significant improvement in the thermal and efficiency performance of the ac/dc power supply when the existing solution was replaced with synchronous rectification using IR1168 and two SO8 MOSFETs. A 1.5% improvement in efficiency and a 25°C cooler temperature for SR MOSFETs were achieved, thus eliminating the heat sink and increasing the reliability of the devices.
Conclusion
A novel control scheme implemented on a single chip facilitates the design of secondary-side synchronous rectification in resonant half-bridge topology and enables manufacturers to further improve the efficiency, thermal, and power-density performance of power converters in the 50 to 200W range, primarily employed in flat-screen TVs, game consoles, laptop adapters, and other home-entertainment applications. In comparison with rectifiers using Schottky diodes, secondary-side synchronous rectification in resonant half-bridge topology using the new control chip offers a 1.5% enhancement in conversion efficiency while keeping the SR MOSFETs 25°C cooler than corresponding diodes, consequently eliminating heat sinks and boosting the power density of the solution and the reliability of the devices.
| Author Information |
 Helen Ding is a senior system and applications engineer at International Rectifier, where she has worked for six years. Her responsibilities include ac/dc power-supply and backlighting-controller product definition and development. Ding has a bachelor's degree in electrical engineering from the University of Electronic Science and Technology of China.
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