Evaluating ESD-protection components: Clamping voltage and dynamic resistance are crucial
A changing product landscape and new designs call for improved protection against ESD strikes on components. A low-voltage device doesn't necessarily have greater protection. Protection comes from low clamping voltage and low dynamic resistance.
By Chi T Hong, California Micro Devices -- EDN, November 26, 2009
Lighter, smaller consumer devices, such as laptops, cell phones, and iPods, use ASICs with geometries as small as 90 nm. At those geometries, even small levels of ESD (electrostatic-discharge)-induced voltage and current can cause catastrophic failure. Other potential sources of ESD strikes are end users who touch I/O connector pins while hot-plugging peripherals using USB (Universal Serial Bus) and HDMI (high-definition-multimedia-interface) connectors. The ESD you generate by walking across a carpet—potentially, a 1-nsec, 30A pulse—is enough to destroy an ASIC. Chip makers are also reducing the standard level of on-chip ESD protection. For these reasons, ESD-protection devices are critical to a design’s success. How do you go about selecting the best ESD-protection device?
Conventional wisdom relies on using IEC (International Electrotechnical Commission) 61000-4-2, which the organization accepted as a standard in 1995. The IEC developed the IEC 61000-4-2 rating test to measure how well a chip could sustain an ESD attack in a finished product-application environment. The standard refers to a contact ESD of 8 kV or an air ESD of 15 kV. The ESD rating on a chip tells you only the amount of voltage that the protection device can survive, however. It does not guarantee that the DUP (device under protection) can survive because you must protect the DUP from residual current when the ESD device cannot shunt most of the peak pulse current to ground. The standard also can’t tell you how much residual current reaches the component. You need to know the ESD device’s clamping voltage and dynamic resistance. Therefore, although it would be simple to specify an ESD-protection device on the basis of the IEC 61000-4-2 rating alone, it’s more difficult to ensure that you’ve protected your design.
During an ESD strike, the ESD-protection device should shunt most of the peak pulse current to ground. However, residual current flows through the DUP, damaging or destroying it (Figure 1). The power across the DUP results from high clamping voltage times high residual-current joule heating due to high dynamic resistance. This combination poses the greatest danger of ESD damage (Figure 2). The peak pulse current equals the shunted current through the ESD device plus the residual current. So the larger the shunt current, the smaller the residual current for a device’s clamping voltage. Also, a device’s shunt resistance equals the clamping voltage divided by the dynamic resistance. In other words, a device’s shunt current and dynamic resistance are inversely proportional to each other. Therefore, an ESD device with a higher dynamic resistance allows more residual current to flow to the DUP.
Dynamic resistance and clamping voltage determine how well an ESD-protection device protects against residual current. During routine operations, the protection device must maintain a high impedance. However, when an ESD strike hits, the protection device rapidly shunts ESD energy to ground. Data sheets may list dynamic resistance. If the data sheet you are looking at doesn’t list this spec, however, you can calculate it from a graph of the device’s clamping voltage versus peak pulse current for IEC 61000-4-2 Level 4, in which the peak pulse current is 30A. Clamping voltage matters more than operating voltage when comparing protection devices. During an ESD strike, an ESD device’s lower clamping voltage minimizes ESD damage due to joule heating. So both a low clamping voltage and low dynamic resistance provide a more accurate metric of how an ESD device will work during a strike (Figure 3).
|
Because dynamic resistance is the yardstick by which you should measure protection devices, the question is how to calculate this parameter if the data sheet does not list it. You can easily calculate dynamic resistance as a slope on a graph of clamping voltage versus peak pulse current, with a peak pulse current of 0, 1, 2, and 3A and so on. After 1A, the slope of dynamic resistance is close to linear. You can also calculate this parameter from clamp-voltage numbers with corresponding peak pulse current because a device’s dynamic resistance is the slope of the graph equal to one clamping voltage minus another clamping voltage divided by the peak pulse current minus another peak pulse current. The formula for determining clamping voltage at a peak pulse current of 30A for IEC 61000-4-2 is to add the breakdown voltage to the peak pulse current and multiply that result by the dynamic resistance.
The residual current flowing through a “protected” chip is proportional to the dynamic resistance of the protection device versus the resistance in the rest of the circuit. Dynamic resistance is the most important factor in determining protection from ESD. All other things being equal, a 5V ESD diode is only marginally better than a 3.3V diode (Table 1). When comparing devices, bear in mind the dynamic resistance, which affects the residual current, rather than the breakdown voltage.
ESD diodes and suppressor/varistors have different performance. Table 2 shows the specs of a system that survived a 12-kV strike using a diode-protection device but failed at 6 kV using a high-dynamic-resistance suppressor. Note that the varistor survived, but the system failed. Note also that both the clamping voltage and the residual current are much higher with varistors.
The availability of two-stage ESD-protection architectures means engineers need not choose between signal integrity and ESD protection. A two-stage ESD architecture offers more protection for a DUP when a single-stage ESD architecture is insufficient for providing lower dynamic resistance and therefore higher residual current. The first stage acts as a traditional ESD device, lowering clamping voltage and dynamic resistance, and the second stage further reduces clamping voltage and residual current (Figure 4).
The fact that a device has low clamping voltage doesn’t mean that it offers higher protection. When creating your design, therefore, the most important parameters for comparison between ESD-protection devices are clamping voltage, dynamic range, and the total number of protection stages in the device. These parameters let you know before you specify an ESD device whether that device is right for your application.
| Acknowledgements | ||
| Thanks go to Allen Tung of California Micro Devices for his help with this article. | ||
