160M-sample/sec, 16-bit dual ADC works in base stations and instrumentation
By Paul Rako, Technical Editor -- EDN, August 17, 2009
National Semiconductor recently announced the low-power, 16-bit, 160M-sample/sec, dual-channel-pipeline ADC16DV160 ADC. The IC features differential inputs and dual-rate LVDS (low-voltage-differential-signaling) outputs. The device operates from 1.8 and 3V supplies, and you can configure it for input ranges of 2.4, 2, 1.5, and 1V p-p. The device achieves an SNR (signal-to-noise ratio) of 76.3 dBFS (decibels relative to full-scale) and an SFDR (spurious-free dynamic range) of 91.2 dBFS when you apply a 197-MHz input signal frequency at ±1-dBFS amplitude. The device has a full-power bandwidth of 1.4 GHz, and its internal reference voltage is 1.2V. Power consumption of both channels together is 1.3W at 160M sample/sec with an input amplitude of −1 dBFS and 100μ-LVDS termination resistors. Communication takes place through an SPI (serial-peripheral interface).
The ADC performs power-up calibration to ensure dynamic performance and to reduce part-to-part variations. You can recalibrate the ADC16DV160 at any time by cycling in and out of the power-down mode. The device also contains an on-chip duty-cycle stabilizer with low additive jitter that allows a wide range of input-clock duty cycles without compromising dynamic performance. The ADC16DV160 comes in a 68-pin LLP package and sells for $140 (1000). Samples and evaluation boards are available; the boards interface directly to the company’s WaveVision 5 software and data-capture board. Production quantities should become available in the late fourth quarter of this year.
