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Voltage doubler improves accuracy

A transistor's low saturation voltage results in less loss.

S Chekcheyev, Tiraspol, Moldova; Edited by Martin Rowe and Fran Granville -- EDN, February 5, 2009

The voltage doubler in Figure 1 provides more accurate voltage doubling than does the conventional voltage doubler in Figure 2 because it uses transistors instead of diodes. You can express the output voltage of the conventional doubler as VOUTDC=2VINAC–2VD, where VOUTDC is the output dc voltage, VINAC is the amplitude of the input ac voltage, and VD is the voltage across the forward-biased diodes. The error of the conventional voltage doubler is 2VD. Transistors Q1 and Q2 in Figure 1 are saturated during the positive and the negative half-cycles, respectively, of the input ac voltage. The operation of the saturated transistors is similar to the operation of the forward-biased diodes in Figure 2. The collector-emitter voltage of the saturated bipolar transistors, however, is substantially smaller than the voltage across the forward-biased diodes. Thus, the error of doubling decreases.

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Transistors Q1 and Q2 are reverse-biased during the negative and the positive half-cycles, respectively. The reverse beta of the bipolar transistors is small; consequently, the operation of the reversed transistors in Figure 1 is similar to the operation of the reverse-biased diodes in Figure 2. Both circuits underwent tests with a resistive load of 10 kΩ and a 50-Hz, 2V-amplitude sinusoidal signal applied to the input. The measured output voltage of the conventional voltage doubler was 2.8V, and the error of doubling was 2×2V–2.8V=1.2V. The measured output voltage of the proposed voltage doubler was 3.8V, and the error of doubling was 2×2V–3.8V=0.2V.

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